DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 629

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.10
The H8/3052BF has a PROM mode as well as the on-board programming modes for programming
and erasing flash memory. In PROM mode, the on-chip ROM can be freely programmed using a
general-purpose PROM writer that supports the Renesas Technology microcomputer device type
with 512-kbyte on-chip flash memory.
18.10.1 Socket Adapters and Memory Map
In PROM mode using a PROM writer, memory reading (verification) and writing and flash
memory initialization (total erasure) can be performed. For these operations, a special socket
adapter is mounted in the PROM writer. The socket adapter product codes are given in table
18.12. In the H8/3052BF PROM mode, only the socket adapters shown in this table should be
used.
2. A RAM area cannot be erased by execution of software in accordance with the erase
3. Block area EB0 includes the vector table. When performing RAM emulation, the
4. Flash write enable (FWE) application and releasing
5. When the emulation function is used, NMI input is prohibited when the P1 bit or E1 bit
Flash Memory PROM Mode
algorithm while flash memory emulation in RAM is being used.
vector table is needed by the overlap RAM.
As in on-board programming mode, care is required when applying and releasing FWE
to prevent erroneous programming or erasing. To prevent erroneous programming and
erasing due to program runaway during FWE application, in particular, the watchdog
timer should be set when the P1 or E1 bit in FLMCR1, or the P2 or E2 bit in FLMCR2,
is set to 1, even while the emulation function is being used. For details, see section
18.11, Flash Memory Programming and Erasing Precautions.
in FLMCR1, or the P2 bit or E2 bit in FLMCR2, is set to 1, in the same way as with
normal programming and erasing. The P1 and E1 bits and the P2 and E2 bits are
cleared by a reset (including a watchdog timer reset), in standby mode, when a high
level is not being input to the FWE pin, or when the SWE1 bit in FLMCR1 is 0, or the
SWE2 bit in FLMCR2 is 0, while a high level is being input to the FWE pin.
Rev. 3.00 Mar 21, 2006 page 599 of 814
REJ09B0302-0300
Section 18 ROM