DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 130

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 5 Interrupt Controller
Figure 5.6 is a flowchart showing how interrupts are accepted when UE = 0.
1. If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an
2. When the interrupt controller receives one or more interrupt requests, it selects the highest-
3. The interrupt controller checks the I bit. If the I bit is cleared to 0, the interrupt request is
4. When an interrupt request is accepted, interrupt exception handling starts after execution of the
5. In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is
6. The I and UI bits are set to 1 in CCR, masking all interrupts except NMI.
7. The vector address of the accepted interrupt is generated, and the interrupt service routine
Rev. 3.00 Mar 21, 2006 page 100 of 814
REJ09B0302-0300
interrupt request is sent to the interrupt controller.
priority request, following the IPR interrupt priority settings, and holds other requests pending.
If two or more interrupts with the same IPR setting are requested simultaneously, the interrupt
controller follows the priority order shown in table 5.3.
accepted regardless of its IPR setting. The value of the UI bit is immaterial. If the I bit is set
to 1 and the UI bit is cleared to 0, only interrupt requests with priority level 1 are accepted;
interrupt requests with priority level 0 are held pending. If the I bit and UI bit are both set to 1,
the interrupt request is held pending.
current instruction has been completed.
saved indicates the address of the first instruction that will be executed after the return from the
interrupt service routine.
starts executing from the address indicated by the contents of the vector address.
a.
Figure 5.5 Interrupt Enable/Disable State Transitions (Example)
All interrupts are
enabled
I
0
Exception handling,
or I
1, UI
c.
All interrupts are
disabled except NMI
I
1
I
1, UI
0
0
UI
0
b.
Only NMI, IRQ , and
IRQ are enabled
Exception handling,
or UI
3
1
2