DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 448

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 Programmable Timing Pattern Controller
Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary Non-
Overlapping Output): Figure 11.7 shows an example of the use of TPC output for four-phase
complementary non-overlapping pulse output.
This operation example is described below.
Rev. 3.00 Mar 21, 2006 page 418 of 814
REJ09B0302-0300
The output trigger ITU channel is set up so that GRA and GRB are output compare registers
and the counter will be cleared by compare match B. The TPC output trigger period is set in
GRB. The non-overlap margin is set in GRA. The IMIEA bit is set to 1 in TIER to enable
IMFA interrupts.
GRB
GRA
H'0000
NDRB
PBDR
TP
TP
TP
TP
TP
TP
TP
TP
15
14
13
12
11
10
9
8
TCNT value
TCNT
(Four-Phase Complementary Non-Overlapping Pulse Output)
95
00
Figure 11.7 Non-Overlapping TPC Output Example
95
65
05
Non-overlap margin
65
59
41
59
56
50
56
95
14
95
65
05
65
Time