DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 342

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 16-Bit Integrated Timer Unit (ITU)
10.1.4
Table 10.3 summarizes the ITU registers.
Table 10.3 ITU Registers
Channel
Common
0
1
Rev. 3.00 Mar 21, 2006 page 312 of 814
REJ09B0302-0300
Register Configuration
H'FF60
Address *
H'FF61
H'FF62
H'FF63
H'FF90
H'FF91
H'FF64
H'FF65
H'FF66
H'FF67
H'FF68
H'FF69
H'FF6A
H'FF6B
H'FF6C
H'FF6D
H'FF6E
H'FF6F
H'FF70
H'FF71
H'FF72
H'FF73
H'FF74
H'FF75
H'FF76
H'FF77
1
Name
Timer start register
Timer synchro register
Timer mode register
Timer function control register
Timer output master enable register
Timer output control register
Timer control register 0
Timer I/O control register 0
Timer interrupt enable register 0
Timer status register 0
Timer counter 0 (high)
Timer counter 0 (low)
General register A0 (high)
General register A0 (low)
General register B0 (high)
General register B0 (low)
Timer control register 1
Timer I/O control register 1
Timer interrupt enable register 1
Timer status register 1
Timer counter 1 (high)
Timer counter 1 (low)
General register A1 (high)
General register A1 (low)
General register B1 (high)
General register B1 (low)
Abbre-
viation
TSTR
TSNC
TMDR
TFCR
TOER
TOCR
TCR0
TIOR0
TIER0
TSR0
TCNT0H
TCNT0L
GRA0H
GRA0L
GRB0H
GRB0L
TCR1
TIOR1
TIER1
TSR1
TCNT1H
TCNT1L
GRA1H
GRA1L
GRB1H
GRB1L
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/(W) *
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/(W) *
R/W
R/W
R/W
R/W
R/W
R/W
2
2
Initial
Value
H'E0
H'E0
H'80
H'C0
H'FF
H'FF
H'80
H'88
H'F8
H'F8
H'00
H'00
H'FF
H'FF
H'FF
H'FF
H'80
H'88
H'F8
H'F8
H'00
H'00
H'FF
H'FF
H'FF
H'FF