DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 45

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Type
Refresh
controller
DMA controller
(DMAC)
16-bit integrated
timer unit (ITU)
Symbol
RFSH
CS
RD
HWR
LWR
DREQ
DREQ
TEND
TEND
TCLKD to
TCLKA
TIOCA
TIOCA
TIOCB
TIOCB
TOCXA
TOCXB
3
1
0
1
0
4
0
4
0
,
,
4
4
to
to
Pin No.
87
88
70
71
72
9, 8
94, 93
96 to 93
4, 2, 99,
97, 95
5, 3, 100,
98, 96
6
7
I/O
Output
Output
Output
Output
Output
Input
Output
Input
Input/
output
Input/
output
Output
Output
Name and Function
Refresh: Indicates a refresh cycle
Row address strobe RAS
strobe signal for DRAM connected to area 3
Column address strobe CAS
address strobe signal for DRAM connected
to area 3; used with 2WE DRAM.
Write enable WE
DRAM connected to area 3; used with
2CAS DRAM.
Upper write UW
DRAM connected to area 3; used with 2WE
DRAM.
Upper column address strobe UCAS
Column address strobe signal for DRAM
connected to area 3; used with 2CAS
DRAM.
Lower write LW
DRAM connected to area 3; used with 2WE
DRAM.
Lower column address strobe LCAS
Column address strobe signal for DRAM
connected to area 3; used with 2CAS
DRAM.
DMA request 1 and 0: DMAC activation
requests
Transfer end 1 and 0: These signals
indicate that the DMAC has ended a data
transfer
Clock input D to A: External clock inputs
Input capture/output compare A4 to A0:
GRA4 to GRA0 output compare or input
capture, or PWM output
Input capture/output compare B4 to B0:
GRB4 to GRB0 output compare or input
capture, or PWM output
Output compare XA4: PWM output
Output compare XB4: PWM output
Rev. 3.00 Mar 21, 2006 page 15 of 814
UW: Write enable signal for
UW
UW
LW: Write enable signal for
LW
LW
WE
WE
WE: Write enable signal for
RAS: Row address
RAS
RAS
Section 1 Overview
REJ09B0302-0300
CAS: Column
CAS
CAS
UCAS:
UCAS
UCAS
LCAS
LCAS:
LCAS