DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 628

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 18 ROM
Example in which Flash Memory Block Area EB0 is Overlapped
1. Set bits RAMS, RAM2 to RAM0 in RAMCR to 1, 0, 0, 0, to overlap part of RAM onto the
2. Real-time programming is performed using the overlapping RAM.
3. After the program data has been confirmed, clear the RAMS bit to release RAM overlap.
4. Write the data written in the overlapping RAM into the flash memory space (EB0).
Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks
Rev. 3.00 Mar 21, 2006 page 598 of 814
REJ09B0302-0300
area (EB0) for which real-time programming is required.
H'7FFFF
H'00000
H'01000
H'02000
H'03000
H'04000
H'05000
H'06000
H'07000
H'08000
regardless of the value of RAM2 to RAM0 (emulation protection). In this state, setting
the P1 or E1 bit in flash memory control register 1 (FLMCR1), or the P2 or E2 bit in
flash memory control register 2 (FLMCR2), will not cause a transition to program
mode or erase mode. When actually programming or erasing a flash memory area, the
RAMS bit should be cleared to 0.
Figure 18.16 Example of RAM Overlap Operation
Flash memory
EB8 to EB15
EB0
EB1
EB2
EB3
EB4
EB5
EB6
EB7
This area can be accessed
from both the RAM area
and flash memory area
On-chip RAM
H'FDF10
H'FE000
H'FEFFF
H'FFF0F