DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 183

MCU 5V 512K 100-TQFP

DF3052BX25V

Manufacturer Part Number
DF3052BX25V
Description
MCU 5V 512K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of DF3052BX25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF3052BX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables the CMI interrupt
requested when the CMF flag is set to 1 in RTMCSR. The CMIE bit is always cleared to 0 when
PSRAME = 1 or DRAME = 1.
Bits 5 to 3—Clock Select 2 to 0 (CKS2 to CKS0): These bits select an internal clock source for
input to RTCNT. When used for refresh control, the refresh controller outputs a refresh request at
periodic intervals determined by compare match between RTCNT and RTCOR. When used as an
interval timer, the refresh controller generates CMI interrupts at periodic intervals determined by
compare match. These bits are write-disabled when the PSRAME bit or DRAME bit is set to 1.
Bits 2 to 0—Reserved: Read-only bits, always read as 1.
7.2.3
RTCNT is an 8-bit readable/writable up-counter.
Bit
Initial value
Read/Write
RTCNT is an up-counter that is incremented by an internal clock selected by bits CKS2 to CKS0
in RTMCSR. When RTCNT matches RTCOR (compare match), the CMF flag is set to 1 and
RTCNT is cleared to H'00.
Bit 6: CMIE
0
1
Bit 5: CKS2
0
1
Refresh Timer Counter (RTCNT)
R/W
7
0
Description
The CMI interrupt requested by CMF is disabled
The CMI interrupt requested by CMF is enabled
Bit 4: CKS1
0
1
0
1
R/W
6
0
R/W
5
0
Bit 3: CKS0
0
1
0
1
0
1
0
1
R/W
4
0
Rev. 3.00 Mar 21, 2006 page 153 of 814
R/W
3
0
Description
Clock input is disabled
/2 clock source
/8 clock source
/32 clock source
/128 clock source
/512 clock source
/2048 clock source
/4096 clock source
R/W
2
0
Section 7 Refresh Controller
R/W
1
0
REJ09B0302-0300
(Initial value)
(Initial value)
R/W
0
0

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