DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 313

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.11.2
Table 9.18 summarizes the registers of port A.
Table 9.18 Port A Registers
Address *
H'FFD1
H'FFD3
Note: * Lower 16 bits of the address.
Port A Data Direction Register (PADDR)
PADDR is an 8-bit write-only register that can select input or output for each pin in port A. When
pins are used for TPC output, the corresponding PADDR bits must also be set.
Bit
Modes
3, 4,
and 6
Modes
1, 2, 5,
and 7
A pin in port A becomes an output pin if the corresponding PADDR bit is set to 1, and an input
pin if this bit is cleared to 0. In modes 3, 4, and 6, PA
address output pin.
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PADDR is initialized to H'00 by a reset and in hardware standby mode in modes 1, 2, 5, and 7.
It is initialized to H'80 by a reset and in hardware standby mode in modes 3, 4, and 6. In software
standby mode it retains its previous setting. If a PADDR bit is set to 1, the corresponding pin
maintains its output state in software standby mode.
Initial value
Read/Write
Initial value
Read/Write
Register Configuration
Name
Port A data direction
register
Port A data register
PA DDR
7
—
W
7
1
0
PA DDR
6
W
W
6
0
0
PA DDR
Abbreviation
PADDR
PADR
5
W
W
5
0
0
Port A data direction 7 to 0
These bits select input or output for port A pins
PA DDR
4
W
W
4
0
0
7
DDR is fixed at 1 and PA
Rev. 3.00 Mar 21, 2006 page 283 of 814
R/W
W
R/W
PA DDR
3
W
W
3
0
0
Modes
1, 2, 5 and 7
H'00
H'00
PA DDR
2
W
W
2
0
0
Initial Value
PA DDR
Section 9 I/O Ports
7
REJ09B0302-0300
functions as an
1
W
W
1
0
0
Modes
3, 4, and 6
H'80
H'00
PA DDR
0
W
W
0
0
0