DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 287

MCU 5V 512K 100-TQFP

DF3052BX25V

Manufacturer Part Number
DF3052BX25V
Description
MCU 5V 512K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of DF3052BX25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF3052BX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Port 3 Data Direction Register (P3DDR)
P3DDR is an 8-bit write-only register that can select input or output for each pin in port 3.
Bit
Initial value
Read/Write
P3DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P3DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. If a P3DDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
Port 3 Data Register (P3DR)
P3DR is an 8-bit readable/writable register that stores output data for pins P3
in P3DDR is set to 1, if port 3 is read the value of the corresponding P3DR bit is returned. When a
bit in P3DDR is cleared to 0, if port 3 is read the corresponding pin level is read.
Bit
Initial value
Read/Write
P3DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Modes 1 to 6 (Expanded Modes)
Port 3 functions as a data bus. P3DDR is ignored.
Mode 7 (Single-Chip Mode)
Port 3 functions as an input/output port. A pin in port 3 becomes an output port if the
corresponding P3DDR bit is set to 1, and an input port if this bit is cleared to 0.
P3 DDR
R/W
P3
7
W
7
0
7
0
7
P3 DDR
R/W
P3
6
W
6
0
6
0
6
P3 DDR
R/W
P3
5
W
5
0
5
0
Port 3 data direction 7 to 0
These bits select input or output for port 3 pins
Port 3 data 7 to 0
These bits store data for port 3 pins
5
P3 DDR
R/W
P3
4
W
4
0
4
0
4
P3 DDR
Rev. 3.00 Mar 21, 2006 page 257 of 814
R/W
P3
3
W
3
0
3
0
3
P3 DDR
R/W
P3
2
W
2
0
2
0
2
P3 DDR
7
R/W
P3
1
W
to P3
Section 9 I/O Ports
1
0
1
0
REJ09B0302-0300
1
0
. When a bit
P3 DDR
R/W
P3
0
W
0
0
0
0
0

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