DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 235

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bits 2 to 0—Data Transfer Select 2B to 0B (DTS2B, DTS1B, DTS0B): These bits select the
data transfer activation source. The selectable activation sources differ between normal mode and
block transfer mode.
The same internal interrupt can be selected to activate two or more channels. The channels are
activated in a priority order, highest priority first. For the priority order, see section 8.4.9, DMAC
Multiple-Channel Operation.
Bit 2:
DTS2B
0
1
Bit 2:
DTS2B
0
1
Normal mode
Block transfer mode
Bit 1:
DTS1B
0
1
0
1
Bit 1:
DTS1B
0
1
0
1
Bit 0:
DTS0B
0
1
0
1
0
1
0
1
Bit 0:
DTS0B
0
1
0
1
0
1
0
1
Auto-request (burst mode)
Cannot be used
Auto-request (cycle-steal mode)
Cannot be used
Cannot be used
Cannot be used
Falling edge of DREQ
Low level input at DREQ
Compare match/input capture A interrupt from ITU
Compare match/input capture A interrupt from ITU
Compare match/input capture A interrupt from ITU
Compare match/input capture A interrupt from ITU
Cannot be used
Cannot be used
Falling edge of DREQ
Cannot be used
Description
Description
channel 0
channel 1
channel 2
channel 3
Rev. 3.00 Mar 21, 2006 page 205 of 814
Section 8 DMA Controller
REJ09B0302-0300
(Initial value)
(Initial value)