DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 73

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.6.5
The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the
byte, then write the byte back. Care is required when these instructions are used to access registers
with write-only bits, or to access ports.
The BCLR instruction can be used to clear flags in the on-chip registers. In an interrupt-handling
routine, for example, if it is known that the flag is set to 1, it is not necessary to read the flag ahead
of time.
Step
1
2
3
In the following example, a BCLR instruction is executed on the data direction register (DDR) of
port 4.
P4
P4
In this example, the BCLR instruction is used to make P4
Before Execution of BCLR Instruction
Input/output
DDR
DR
Execution of BCLR Instruction
BCLR
After Execution of BCLR Instruction
Input/output
DDR
DR
7
5
and P4
to P4
#0, @P4DDR
Read
Bit manipulation
Write
0
Notes on Use of Bit Manipulation Instructions
are set as output pins, and are in the low-level output state.
6
are set as input pins, and are inputting low-level and high-level signals, respectively.
P4
Input
0
1
P4
Output
1
1
7
7
P4
Input
0
0
P4
Output
1
0
; Execute BCLR instruction on DDR
6
6
Description
Read data (byte unit) at the specified address
Modify the specified bit in the read data
Write the modified data (byte unit) to the specified address
P4
Output
1
0
P4
Output
1
0
5
5
P4
Output
1
0
P4
Output
1
0
4
4
0
Rev. 3.00 Mar 21, 2006 page 43 of 814
an input port.
P4
Output
1
0
P4
Output
1
0
3
3
P4
Output
1
0
P4
Output
1
0
2
2
P4
Output
1
0
P4
Output
1
0
REJ09B0302-0300
1
1
Section 2 CPU
P4
Output
1
0
P4
Input
0
0
0
0