DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 240

MCU 5V 512K 100-TQFP

DF3052BX25V

Manufacturer Part Number
DF3052BX25V
Description
MCU 5V 512K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of DF3052BX25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF3052BX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 8 DMA Controller
For the detailed settings see section 8.2.4, Data Transfer Control Registers (DTCR).
Figure 8.3 shows a sample setup procedure for I/O mode.
8.4.3
Idle mode can be selected independently for each channel.
One byte or word is transferred at each transfer request in idle mode. A designated number of
these transfers are executed. One address is specified in the memory address register (MAR), the
other in the I/O address register (IOAR). The direction of transfer is determined automatically
from the activation source. The transfer is from the address specified in IOAR to the address
specified in MAR if activated by an SCI channel 0 receive-data-full interrupt, and from the
address specified in MAR to the address specified in IOAR otherwise.
Table 8.7 indicates the register functions in idle mode.
Rev. 3.00 Mar 21, 2006 page 210 of 814
REJ09B0302-0300
destination addresses
Idle Mode
Set transfer count
I/O mode setup
Set source and
Read DTCR
Set DTCR
I/O mode
Figure 8.3 I/O Mode Setup Procedure (Example)
1
2
3
4
1. Set the source and destination addresses
2. Set the transfer count in ETCR.
3. Read DTCR while the DTE bit is cleared
4. Set the DTCR bits as follows.
in MAR and IOAR. The transfer direction
is determined automatically from the
activation source.
to 0.
• Select the DMAC activation source
• Set or clear the DTIE bit to enable or
• Clear the RPE bit to 0 to select I/O
• Select MAR increment or decrement
• Select byte size or word size with the
• Set the DTE bit to 1 to enable the
with bits DTS2 to DTS0.
disable the CPU interrupt at the end of
the transfer.
mode.
with the DTID bit.
DTSZ bit.
transfer.

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