DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 458

MCU 5V 512K 100-TQFP

DF3052BX25V

Manufacturer Part Number
DF3052BX25V
Description
MCU 5V 512K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of DF3052BX25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF3052BX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 12 Watchdog Timer
12.2.3
RSTCSR is an 8-bit readable/writable *
generated by watchdog timer overflow.
Bit
Initial value
Read/Write
Bit 7 is initialized by input of a reset signal at the RES pin. It is not initialized by reset signals
generated by watchdog timer overflow.
Notes: 1. RSTCSR differs from other registers in being more difficult to write. For details see
Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that
TCNT has overflowed and generated a reset signal. This reset signal resets the entire chip
internally.
Rev. 3.00 Mar 21, 2006 page 428 of 814
REJ09B0302-0300
Bit 7: WRST
0
1
2. Only 0 can be written in bit 7, to clear the flag.
3. Do not set bit 6 to 1.
Reset Control/Status Register (RSTCSR)
section 12.2.4, Notes on Register Access.
Watchdog timer reset
Indicates that a reset signal has been generated
R/(W)
WRST
7
0
Description
[Clearing conditions]
[Setting condition]
Set when TCNT overflow generates a reset signal during watchdog timer
operation
*
2
Reserved bit
Must not be set to 1
Cleared to 0 by reset signal input at RES pin
Cleared by reading WRST when WRST = 1, then writing 0 in WRST
6
0
1
5
1
register that monitors the state of the reset signal
*3
4
1
Reserved bits
3
1
2
1
1
1
(Initial value)
0
1

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