DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 361

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

When bit TPSC2 is cleared to 0 an internal clock source is selected, and the timer counts only
falling edges. When bit TPSC2 is set to 1 an external clock source is selected, and the timer counts
the edge or edges selected by bits CKEG1 and CKEG0.
When channel 2 is set to phase counting mode (MDF = 1 in TMDR), the settings of bits TPSC2 to
TPSC0 in TCR2 are ignored. Phase counting takes precedence.
10.2.11 Timer I/O Control Register (TIOR)
TIOR is an 8-bit register. The ITU has five TIORs, one in each channel.
Channel
0
1
2
3
4
Bit
Initial value
Read/Write
Each TIOR is an 8-bit readable/writable register that selects the output compare or input capture
function for GRA and GRB, and specifies the functions of the TIOCA and TIOCB pins. If the
output compare function is selected, TIOR also selects the type of output. If input capture is
selected, TIOR also selects the edge or edges of the input capture signal.
TIOR is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: Read-only bit, always read as 1.
Reserved bit
Abbreviation
TIOR0
TIOR1
TIOR2
TIOR3
TIOR4
—
—
7
1
I/O control B2 to B0
These bits select GRB functions
IOB2
R/W
6
0
Function
TIOR controls the general registers. Some functions differ in
PWM mode. TIOR3 and TIOR4 settings are ignored when
complementary PWM mode or reset-synchronized PWM mode
is selected in channels 3 and 4.
IOB1
R/W
5
0
IOB0
R/W
4
0
Section 10 16-Bit Integrated Timer Unit (ITU)
Reserved bit
Rev. 3.00 Mar 21, 2006 page 331 of 814
—
—
3
1
IOA2
R/W
I/O control A2 to A0
These bits select GRA
functions
2
0
IOA1
R/W
1
0
REJ09B0302-0300
IOA0
R/W
0
0