DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 151

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.3.2
For each of areas 7 to 0, the H8/3052BF can output a chip select signal (CS
to indicate when the area is selected. Figure 6.3 shows the output timing of a CS
0).
Output of CS
(DDR) of the corresponding port.
In the expanded modes with on-chip ROM disabled, a reset leaves pin CS
pins CS
DDR bits must be set to 1. In the expanded modes with on-chip ROM enabled, a reset leaves pins
CS
must be set to 1. For details see section 9, I/O Ports.
Output of CS
register (CSCR). A reset leaves pins CS
CS
When the on-chip ROM, on-chip RAM, and on-chip registers are accessed, CS
high. The CS
signals for SRAM and other devices.
3
7
to CS
to CS
3
to CS
Chip Select Signals
0
4
, the corresponding CSCR bits must be set to 1. For details see section 9, I/O Ports.
CS
CS
CS
CS
CS
CS
in the input state. To output chip select signals CS
n
3
7
signals are decoded from the address signals. They can be used as chip select
1
to CS
to CS
in the input state. To output chip select signals CS
Address
bus
CS
CS
CS
CS
CS
CS
CS
n
0
4
: Output of CS
: Output of CS
Figure 6.3 CS
3
7
to CS
to CS
CS
CS
CS
7
to CS
n
Output Timing (n = 7 to 0)
0
4
is enabled or disabled in the data direction register
is enabled or disabled in the chip select control
External address in area n
4
in the input state. To output chip select signals
Rev. 3.00 Mar 21, 2006 page 121 of 814
3
, to CS
3
, to CS
0
the corresponding DDR bits
Section 6 Bus Controller
0
1
in the output state and
7
the corresponding
to CS
7
REJ09B0302-0300
n
and CS
signal (n = 7 to
0
) that goes low
0
remain