DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 212

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 Refresh Controller
7.4
Compare match interrupts (CMI) can be generated when the refresh controller is used as an
interval timer. Compare match interrupt requests are masked/unmasked with the CMIE bit of
RTMCSR.
7.5
When using the DRAM or pseudo-static RAM refresh function, note the following points:
With the refresh controller, if directly connected DRAM or PSRAM is disconnected*, the
P8
simultaneously.
Note: * When the DRAM enable bit (DRAME) or PSRAM enable bit (PSRAME) in the refresh
Refresh cycles are not executed while the bus is released, during software standby mode, and
when a bus cycle is greatly prolonged by insertion of wait states. When these conditions occur,
other means of refreshing are required.
If refresh requests occur while the bus is released, the first request is held and one refresh cycle is
executed after the bus-released state ends. Figure 7.24 shows the bus cycles in this case.
Rev. 3.00 Mar 21, 2006 page 182 of 814
REJ09B0302-0300
0
Address bus
P8
P8
/RFSH/IRQ
0
1
/RFSH/IRQ
/CS
control register (RFSHCR) is cleared to 0 after being set to 1.
Usage Notes
Interrupt Source
3
/IRQ
Figure 7.23 Operation when DRAM/PSRAM Connection Is Switched
0
1
pin and the P8
0
1
/CS
3
/IRQ
1
pin may both become low-level outputs
Area 3 start address