TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 100
TX4939XBG-400
Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet
1.TX4939XBG-400.pdf
(740 pages)
Specifications of TX4939XBG-400
Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456
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CG
The ideal value of Multiply-Divider for this PLL is "625/7065" (n=625, d=7065). However, this value of multiply-divider
would create undesirable phase jitter with very low frequency element. Therefore, the actual circuit uses "19/429" in stead.
This approximation has -11.2 PPM error against target frequency of 451,584,000 Hz. Table 5-4 shows those actual
frequencies.
It is the fact that the fractional N PLL might generate clock with some level of jitter. However, it depends on the application
if this jitter value would be acceptable or not. In the case that the application required very clean clocks, this PLL should
have alternate PLL mode, such as Integer PLL. Since 19/429 is about 1/22, the integer multiplier is better to close to 22.
In this design, X20 is chosen for that mode. In this mode, 20 MHz external clock should be changed to 22.5792 MHz
instead. This clock can be available from any of Audio Clock Generator.
Rev. 3.1 November 1, 2005
Sampling Clock
921,600 Hz
96,000 Hz
88,200 Hz
48,000 Hz
44,100 Hz
32,000 Hz
24,000 Hz
22,050 Hz
16,000 Hz
8,000 Hz
Target
Table 5-4 Frequency Error in the Final Clocks
Result Logic Clock
49.151450 MHz
45.157895 MHz
24.575725 MHz
22.578947 MHz
16.383817 MHz
12.287863 MHz
11.289474 MHz
14.745435 MHz
8.191908 MHz
4.09599 MHz
5-6
Sampling Clock
921,589.69 Hz
95,998.93 Hz
88,199.01 Hz
47,999.46 Hz
44,099.51 Hz
31,999.64 Hz
23,999.73 Hz
22,049.75 Hz
15,999.82 Hz
7,999.98 Hz
Actual
Toshiba RISC Processor
TX4939
5
5
5
5
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