TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 412

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
16.4.26. PCI Bus Arbiter Broken Master Register (PBABM)
This register indicates the acknowledged Broken Master. This register sets the bit that corresponds to the PCI Master device
that was acknowledged as the Broken Master when the Broken Master Check Enable bit (BMCEN) in the PCI Bus Arbiter
Configuration Register (PBACFG) is set.
Regardless of the value of the Broken Master Check Enable bit, a PCI Master device is removed from the arbitration scheme
when “1” is written to the corresponding BM bit.
This register must be cleared to “0” since bit mapping changes, making this register value invalid when the PCI Bus Arbiter
Request Port Register (PBAREQPORT) is changed.
This register is only valid when using the on-chip PCI Bus Arbiter.
Rev. 3.1 November 1, 2005
Default
Default
NAME
NAME
Bit
31:8
7
6
5
4
3
2
1
0
TYPE
TYPE
Mnemonic
BM_A
BM_B
BM_C
BM_D
BM_W
BM_X
BM_Y
BM_Z
31
15
30
14
Field Name
Rsvd
Broken Master
Broken Master
Broken Master
Broken Master
Broken Master
Broken Master
Broken Master
Broken Master
29
13
Figure 16-37 PCI Bus Arbiter Broken Master Register
Table 16-38 PCI Bus Arbiter Broken Master Register
RESERVED
28
12
27
11
Description
Broken Master A (Default: 0)
Indicates whether PCI Bus Master A is a Broken Master.
1: PCI Bus Master A was acknowledged as a Broken Master.
0: PCI Bus Master A was not acknowledged as a Broken Master.
Broken Master B (Default: 0)
Indicates whether PCI Bus Master B is a Broken Master.
1: PCI Bus Master B was acknowledged as a Broken Master.
0: PCI Bus Master B was not acknowledged as a Broken Master.
Broken Master C (Default: 0)
Indicates whether PCI Bus Master C is a Broken Master.
1: PCI Bus Master C was acknowledged as a Broken Master.
0: PCI Bus Master C was not acknowledged as a Broken Master.
Broken Master D (Default: 0)
Indicates whether PCI Bus Master D is a Broken Master.
1: PCI Bus Master D was acknowledged as a Broken Master.
0: PCI Bus Master D was not acknowledged as a Broken Master.
Broken Master W (Default: 0)
Indicates whether PCI Bus Master W is a Broken Master.
1: PCI Bus Master W was acknowledged as a Broken Master.
0: PCI Bus Master W was not acknowledged as a Broken Master.
Broken Master X (Default: 0)
Indicates whether PCI Bus Master X is a Broken Master.
1: PCI Bus Master X was acknowledged as a Broken Master.
0: PCI Bus Master X was not acknowledged as a Broken Master.
Broken Master Y (Default: 0)
Indicates whether PCI Bus Master Y is a Broken Master.
1: PCI Bus Master Y was acknowledged as a Broken Master.
0: PCI Bus Master Y was not acknowledged as a Broken Master.
Broken Master Z (Default: 0)
Indicates whether PCI Bus Master Z is a Broken Master.
1: PCI Bus Master Z was acknowledged as a Broken Master.
0: PCI Bus Master Z was not acknowledged as a Broken Master.
26
10
25
9
16-48
RESERVED
24
8
BM_A BM_B BM_C BM_D BM_W BM_X BM_Y BM_Z
23
7
22
6
21
5
20
Toshiba RISC Processor
4
0x00
R/W
19
3
18
2
17
1
R/W
⎯
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TX4939
16
0
16
16