TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 20

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Index
Rev. 3.1 November 1, 2005
Figure 16-72 PDMAC Control Register .............................................................................................................. 16-79
Figure 16-73 Status Register .............................................................................................................................. 16-81
Figure 16-74 PDMAC Interrupt Signaling ........................................................................................................... 16-83
Figure 16-75 Memory Space (m) Lower Base Address Register ......................................................................... 16-85
Figure 16-76 IO Space Base Address Register ................................................................................................... 16-86
Figure 16-77 Capability ID Register..................................................................................................................... 16-86
Figure 16-78 Next Item Pointer Register ............................................................................................................. 16-86
Figure 16-79 PMC Register ................................................................................................................................. 16-87
Figure 16-80 PMCSR Register ............................................................................................................................ 16-88
Figure 17-1 ATA100 Controller Block Diagram ...................................................................................................... 17-2
Figure 17-2 Command Register ............................................................................................................................ 17-5
Figure 17-3 Status Register ................................................................................................................................... 17-5
Figure 17-4 PRD Table Pointer Register................................................................................................................ 17-6
Figure 17-5 PRD Configuration ............................................................................................................................. 17-7
Figure 17-6 System Control Register .................................................................................................................... 17-8
Figure 17-7 Transfer Word Count 1 Register....................................................................................................... 17-10
Figure 17-8 Transfer Word Count 2 Register........................................................................................................17-11
Figure 17-9 Additional Control Register............................................................................................................... 17-13
Figure 17-10 Lower Burst Count Register ........................................................................................................... 17-14
Figure 17-11 Upper Burst Count Register............................................................................................................ 17-14
Figure 17-12 Data Register ATA Shadow ............................................................................................................ 17-15
Figure 17-13 Error/Feature Register ATA Shadow............................................................................................... 17-15
Figure 17-14 Sector Count Register ATA Shadow ............................................................................................... 17-15
Figure 17-15 LBA Low Register ATA Shadow...................................................................................................... 17-15
Figure 17-16 LBA Mid Register ATA Shadow....................................................................................................... 17-16
Figure 17-17 LBA High Register ATA Shadow ..................................................................................................... 17-16
Figure 17-18 Device Register ATA Shadow ......................................................................................................... 17-16
Figure 17-19 Command/Status Register ATA Shadow......................................................................................... 17-17
Figure 17-20 Alternate Status Register ATA Shadow ........................................................................................... 17-17
Figure 17-21 PIO Access Address Register ........................................................................................................ 17-17
Figure 17-22 Host Reset Timer Register ............................................................................................................. 17-18
Figure 17-23 Interrupt Control Register ............................................................................................................... 17-19
Figure 17-24 ATAPI Packet Command Register.................................................................................................. 17-21
Figure 17-25 Bus Transfer Count High Register.................................................................................................. 17-21
Figure 17-26 Bus Transfer Count Low Register................................................................................................... 17-22
Figure 17-27 ATA Device Timing Error Register .................................................................................................. 17-22
Figure 17-28 Packet Transfer Control Register ................................................................................................... 17-23
Figure 18-1 System Level block diagram of Quad eMAC in TX4939..................................................................... 18-2
Figure 18-2 Ethernet Controller Block Diagram ..................................................................................................... 18-3
Figure 18-3 Data Structure Outline ....................................................................................................................... 18-8
Figure 18-4 DMA Function Block ........................................................................................................................ 18-10
Figure 18-5 MAC Function Block........................................................................................................................ 18-12
Figure 18-6 FDNext Field ................................................................................................................................... 18-16
Figure 18-7 FDCtl Field ...................................................................................................................................... 18-17
Figure 18-8 BDCtl Field ....................................................................................................................................... 18-18
Figure 18-9 BDStat Field .................................................................................................................................... 18-19
Figure 18-10 Ethernet Packet Frame Fields ....................................................................................................... 18-20
Figure 18-11 Format of Recipient Addresses...................................................................................................... 18-21
Figure 18-12 Transmission with no Collisions..................................................................................................... 18-24
Figure 18-13 Transmission when Collision Occurred in the Preamble ............................................................... 18-24
Figure 18-14 ARM Memory Map......................................................................................................................... 18-26
Figure 18-15 Address Map of PCI Configuration Registers ................................................................................ 18-37
Figure 18-16 Address Map of DMA Control, Status Registers ............................................................................ 18-37
Figure 18-17 Address Map of Flow Control Registers ........................................................................................ 18-37
Figure 18-18 Address Map of MAC Control, Status Registers ............................................................................ 18-37
Figure 18-19 Vendor ID Register ........................................................................................................................ 18-38
Figure 18-20 Device ID Register ........................................................................................................................ 18-38
Figure 18-21 PCI Command Register ................................................................................................................ 18-39
Figure 18-22 PCI Status Register ....................................................................................................................... 18-40
Figure 18-23 Class Code Register ..................................................................................................................... 18-41
Figure 18-24 PCI Control Register ..................................................................................................................... 18-42
Figure 18-25 I/O Base Address Register ............................................................................................................ 18-43
Figure 18-26 Memory Base Address Register .................................................................................................... 18-43
Figure 18-27 Subsystem Vendor ID Number Register........................................................................................ 18-44
Figure 18-28 Subsystem ID Register.................................................................................................................. 18-44
Figure 18-29 PCI Function Pointer Register ....................................................................................................... 18-45
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Toshiba RISC Processor
TX4939