TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 206

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EBC
Rev. 3.1 November 1, 2005
Bit
63:48
47:23
22
47:21
20
19:18
17:16
15:12
Mnemonic
BA[35:20]
ISA
BSZ
PM
PWT
WT
Field Name
Base Address
Reserved
ISA Mode
Reserved
Bus Width
Page Mode
Page Size
Page
time
Normal Mode Wait
Time
Mode
Table 9-8 External Bus Channel Control Register
Wait
Description
External Bus Control Base Address (Default: 0x01FC/0x0000)
A physical address is used to specify the base address. The upper 16
bits [35:20] of the physical address are compared to the value of this
field.
ISA Mode Set (Default: 0)
Specifies the ISA-16 Mode.
0: ISA Mode Disable
1: ISA Mode Enable
External Bus Control Bus Size (Default: SADB[3]/0)
Specifies the memory bus width.
0: 16-bit width
1: 8-bit width
Note: SADB[3] is set to Channel 0 as the default.
External Bus Control Page Mode Page Size (Default: 00)
Specifies the Page mode (Page mode memory support) use and
page size.
00: Normal mode
01: 4-page mode
10: 8-page mode
11: 16-page mode
External Bus Control Page Mode Wait Time (Channel 0=2’b11 / 00)
Specifies the wait cycle count during Burst access when in the Page
mode.
00: 0 wait cycles
01: 1 wait cycle
Specifies a wait cycle count from 0 to 62 that matches WT when in the
Normal mode or Ready mode. (See the WT item.)
External Bus Control Normal Mode Wait Time
(Default: [111 (~SADB[2]])/[0000])
Specifies the wait cycle count in the first cycle of a Single Cycle or
Burst access.
Specifies the following wait cycle count when in the Page mode.
0000: 0 wait cycles
1000: 8 wait cycles
0001: 1 wait cycle
1001: 9 wait cycles
0010: 2 wait cycles
1010: 10 wait cycles 1110: 14 wait cycles
0011: 3 wait cycles
1011: 11 wait cycles 1111: 15 wait cycles
Specifies a wait cycle count from 0 to 62 that matches PWT when in a
mode other than the Page mode.
PWT[1:0]: WT[3:0]
000000: 0 wait cycles
000001: 1 wait cycles
000011: 3 wait cycles
001110: 14 wait cycles
001111: 15 wait cycles
011110: 30 wait cycles
011111: 31 wait cycles
111111: External ACK mode
Note 1: Value that is the reverse of SA[2] is set to the LSB of Channel
0 as the default.
Note 2: If PWT:WT is set to 0x3f when PM = 00 and RDY = 0, the
external bus enters the ACK* Input mode (External ACK mode)
without the wait cycle count for the ACK* output being the maximum
value.
Note 3: WT[0] is used to select Dynamic/Static ACK*/Ready mode
when in the Ready mode. Therefore, the Wait cycle count is an even
number.
Note 4: Set the WT wait cycle count to a value greater than the PWT
Wait cycle count when in the Page mode.
: :
: :
9-16
10: 2 wait cycles
11: 3 wait cycles
0100: 4 wait cycles
1100: 12 wait cycles
0101: 5 wait cycles
1101: 13 wait cycles
0110: 6 wait cycles
0111: 7 wait cycles
Toshiba RISC Processor
R/W
R/W
⎯
R/W
⎯
R/W
R/W
R/W
R/W
TX4939
9
9