TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 294

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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Toshiba RISC Processor
DMA
TX4939
When the Chain End bit (CHDN) is set, the DMADONE* signal is only asserted when the DMAACK[n] signal for the last
DMA transfer in the Link List Command Chain is asserted.
When the Chain End bit (CHDN) is cleared, the DMADONE* signal is asserted when the DMAACK[n] signal for the last data
transfer in a DMA transfer specified by the current DMA Channel Register is asserted. Namely, if the Link List Command
chain is used, there is one assertion at the end of each data transfer specified by each Descriptor.
If the DMADONE* signal is set to be used as an input signal (DMCCRn.DNCTRL = 01/11), DMA transfer can be set to end
normally when the external device asserts the DMADONE* signal when the DMAACK[n] signal of channel n is asserted.
DMADONE* is asserted during DMAACK[n] is not asserted, then unexpected operation occurs. When DMA transfer is
terminated by the DMADONE* assertion of the external device, the External DONE Assert bit (DMCSRn.EXTDN) of the
DMA Channel Status Register is set regardless of the setting of the Chain End bit (CHDN) of the DMA Channel Control
Register (DMCCRn). Operation is as follows depending on the setting of the Chain End bit (CHDN).
When the Chain End bit (CHDN) is set, all DMA transfer for that chain is terminated. At this time, the Normal Chain End bit
(NCHNC) and the Normal Transfer End bit (NTRNFC) of the DMA Channel Status Register are both set and the Transfer
Active bit (DMCCRn.XFACT) of the DMA Channel Control Register is cleared.
When the Chain End bit (CHDN) is cleared, only DMA transfer specified by the current DMA Channel Register ends
normally, and only the Normal Transfer End bit (NTRNFC) is set. When the Chain Enable bit (CHNEN) of the DMA Channel
Control Register (DMCCRn) is set, chain transfer is executed and DMA transfer continues. When the Chain Enable bit
(CHNEN) is cleared, the Transfer Active bit (DMCCRn.XFACT) is cleared and the Normal Chain End bit (NCHNC) is set.
Three clock cycles are required from external assertion of the DMADONE* signal to disabling of new DMA access.
Operation will not stop even if the bus operation in progress is a Single transfer or a Burst transfer. For example, if the
DMADONE* signal is asserted during Read operation of Dual Address transfer, the corresponding Write bus operation will
also be executed.
If the DMADONE* pin is set to become both input and output for channel n (DMCCRn.DNCTRL = “11”), the DMADONE*
signal becomes an open drain signal when the channel becomes active. When used by this mode, the DMADONE* signal
must be pulled up by an external source. When in this mode, the External DONE Assert bit (DMCSRn.EXTDN) is not only
set when asserted by an external device, but is also set when asserted by the TX4939.
14.3.4. Internal I/O DMA Transfer Mode
14
14
Performs DMA with the on-chip Serial I/O Controller, the AC-link Controller or the I2S Controller. Set the DMA Channel
Control Register (DMCCRn) as follows.
DMCCRn.EXTRQ = 1: I/O DMA Transfer mode
DMCCRn.SNGAD = 0: Dual Address Transfer
Refer to “14.3.8 Dual Address Transfer” and “DMA transfer (Serial I/O Controller)” or “DMA operation (AC-link Controller)”
or “DMA Interface (I2S Controller)” for more information.
Refer to the Boot Configuration section for selection AC-link or I2S
Performs DMA with the on chip NAND Flash Memory Controller (NDFMC) Set the DMA Channel 3 Control Register
(DMCCRn) as follows.
DMCCRn.EXTRQ = 1: I/O DMA Transfer mode
DMCCRn.SNGAD = 1: Single Address Transfer
Refer to DMA Operation section in NDFMC for more information
Rev. 3.1 November 1, 2005
14-6

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