TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 350

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

DDR
DDR_CTL_04 = 0x8020
DDR_CTL_05 = 0x8028
DDR_CTL_06 = 0x8030
Rev. 3.1 November 1, 2005
Name
MAX_CS_REG
-
INITAREF
-
Name
MAX_ROW_REG
-
MAX_COL_REG
-
Name
CASLAT_LIN
-
CASLAT
-
Bits
1:0
7:2
11:8
15:12
Bits
3:0
7:4
11:8
15:12
Bits
3:0
7:4
10:8
15:11
Default
0x2
-
0x0
-
Default
0xe
-
0xc
-
Default
0x0
-
0x0
-
Range
0x2
-
0x0-0xf
-
Range
0xe
-
0xc
-
Range
0x0-0xf
-
0x0-0x7
-
15-20
Description
Maximum number of chip selects available.
Maximum number of chip selects configured for the controller. This
value can be used to set the CS_diff.
CS_diff = Max_cs_reg - <number of ranks of memory connected to
the controller>
The number of ranks of memory must be a power of 2.
READONLY
Reserved
Number of autorefresh commands to execute during initialization of
DRAMS.
The number of auto-refresh commands needed by the DRAM
devices to satisfy the initialization sequence.
Reserved
Description
Maximum width of memory address bus.
Maximum number of row bits configured for the controller. This
value can be used to set the Addr_pins.
Addr_pins = Max_row_reg - <number of row bits in memory device>
READONLY
Reserved
Maximum width of column address in DRAMs.
Maximum number of column bits configured for the controller. This
value can be used to set the Column_size.
Column_size = Max_col_reg - <number of column bits in memory
device>
READONLY
Reserved
Description
Cas latency in half cycles.
Cas Latency linear value. This field encodes the actual cas latency
in ½ cycle increments.
0000 - 0010 RESERVED
0011 = 1.5 cycles
0100 = 2 cycles
0101 = 2.5 cycles
0110 = 3 cycles
0111 = 3.5 cycles
1000 = 4 cycles
1001-1111 RESERVED
Reserved
Encoded cas latency sent to DRAMs during initialization.
Cas Latency encoding to be programmed into the DRAMs upon
initialization. Please refer to the encoding specified in the DRAM
spec sheet. This encoding should correspond to the Caslat_Linear
setting. See the regconfig files in the release for actual settings for
each particular device.
Reserved
Toshiba RISC Processor
TX4939
15
15