TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 507

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
18.3.7. Memory configuration
This subsection describes the data structure the PCI-mounted Ethernet Controller uses when exchanging data with the
Host system. The data structures are stored in system memory. There are three basic data structures:
These data structures are used in the following manners:
Figure 18-3 shows an outline of each data structure. This subsection describes each data structure in detail. Depending
on the type of data structure, some queues in use may include different information. Each following item will describes
this in detail. During continuous polling operation, a queue never becomes empty once it is created. One frame descriptor
is always appended to the end of a queue. This dummy frame descriptor is used in processes that generate a descriptor
to be transmitted. For details, see 18.3.9 DMA Operation. To start transmission, the system sets the address of the first
frame descriptor in the Transmission queue in the Transmission Frame Pointer Register. The Ethernet Controller
transmits while tracing the Transmission queue, then updates the status of the transmitted packet. The owner bit of the
Frame Descriptor Status Field and Frame Descriptor Control field indicates “Transmission complete”. This enables the
system software to handle the queue in situations such as when releasing the buffer. The Ethernet Controller fetches the
buffer from the buffer list, and then writes the new frame descriptor or new buffer descriptor in a free descriptor area.
Subsection 18.3.9 DMA operation describes this.
18.3.7.1. Frame descriptor
A frame descriptor consists of a pointer to the next frame descriptor in the queue, a System Data field, a Frame Length
field, a Control field, and a Status field.
Table 18-3 shows the frame descriptor format.
The Ethernet Controller retains the Frame System Data field (FDSystem). The FDSystem field can be used by system or
application programs. The initial value of the frame descriptor written to the Reception queue is fetched from the frame
descriptor of the current buffer list.
Depending on the queue type, the usage of the FDNext, FDCtl, FDStat, or FDLength fields varies. See the following
items for an explanation.
Rev. 3.1 November 1, 2005
Frame descriptor
Buffer descriptor
Data buffer
Transmission queue:
Reception queue:
Buffer list:
FDSystem
FDLength
FDNext
FDStat
FDCtl
Byte 3
FDCtl
Frame descriptor control
Frame descriptor status
Frame descriptor length
Next frame descriptor
Frame system data
Byte 2
Table 18-3 Frame Descriptor Format
Listing the frame descriptors that have unused buffers for
Listing the frame descriptors of packets ready for transmission
Listing the frame descriptors of received packets
receiving data
FDSystem
FDNext
FDStat
18-15
Byte 1
Is used by the system or application software
Address of the next frame descriptor in the
Field that expresses the length of this field
FDLength
Control field of this frame descriptor
Status field of this frame descriptor
Byte 0
queue
Toshiba RISC Processor
Offset
0C h
00 h
04 h
08 h
TX4939
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