TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 195

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EBC
9.2.7.
The following four modes are available as controller access modes.
These modes can be set separately for each channel.
Depending on the combination of modes in each channel, either of two modes in which the ACK*/Ready signal operates
differently (ACK*/Ready Dynamic mode, ACK*/Ready Static mode) is selected by the ACK*/Ready Mode bit
(CCFG.ARMODE) of the Chip Configuration Register. The mode selected is applied globally to all channels.
Access using Burst transfer by the internal bus (G-Bus) is supported when in a mode other than the Ready mode. However,
the Ready mode is not supported.
Rev. 3.1 November 1, 2005
(1)
(2)
Dynamic Mode
ACK*/Ready
ACK*/Ready
Static Mode
Normal mode
Page mode
External ACK mode
Ready mode
Access Mode
ACK*/READY Dynamic mode (CCFG.ARMODE = 0)
This mode is selected in the initial state.
The ACK*/Ready signal automatically switches to either input or output according to the setting of each
channel. When in the Normal mode or the Page mode, the ACK*/Ready signal is an output signal, and the
internally generated ACK* signal is output. When in the External ACK* or Ready mode, the ACK*/Ready
signal becomes an input signal. The ACK*/Ready signal outputs High if there is no access to the External
Bus Controller. However, this signal may output Low during access to SDRAM.
ACK*/Ready Static mode (CCFG.ARMODE = 0)
The internally generated ACK* signal is not output when in either the Normal mode or Page mode.
Therefore, the ACK*/Ready signal will not become an output in any channel.
PM
!0
!0
0
0
RDY
0
1
0
1
0
1
0
1
PWT:WT
!3f
!3f
⎯
⎯
⎯
⎯
⎯
⎯
3f
3f
Table 9-6 Operation Mode
External ACK*
External ACK*
Reserved
Reserved
READY
READY
Normal
Normal
Mode
Page
Page
9-5
ACK*/READY
Pin State
Output
Output
Input
Input
Input
Input
Hi-Z
Hi-Z
⎯
⎯
Generated ACK*
Generated ACK*
Generated ACK*
Generated ACK*
Timing State
Access End
Ready Input
Ready Input
ACK* Input
ACK* Input
Toshiba RISC Processor
Internally
Internally
Internally
Internally
⎯
⎯
G-Bus Burst
Access
⎯
⎯
⎯
⎯
√
√
√
√
√
√
TX4939
9
9