TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 692

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

CRYPT
26.2. CIPHER Theory of Operations
Cipher controller supports three types of encryption. They are DES, 3DES and AES algorithms.
Cipher controller also supports two types of hash algorithms. They are MD5 and SHA1.
Cipher controller can perform the following:
When hash engine is enabled, hash output data length is different for MD5 and SHA1.
Cipher controller continuously operates and stops after the completion of the descriptor with Next descriptor address = Null.
All Input/Output byte count (IbyteCount/ObyteCount) must be “0” or at least “8 bytes”.
Message of 0 byte count is not supported for hashing.
26.2.1. XOR Function
In the Cipher controller, there are two XOR modes. Mode 0 is to XOR the memory data with a 64 bit register data. Mode
1 is to XOR two memory data and output back the result back to memory location.
Rev. 3.1 November 1, 2005
Mode 0:
Mode 1:
a)
b)
c)
-
-
DES
AES
Only encrypt/decrypt (either using DES, 3DES, or AES algorithm)
Only hash (either using MD5 or SHA1 algorithm)
Encrypt/Decrypt and hash together (either DES, 3DES or AES with either MD5 or SHA1)
For MD5, hash output data is 128 bits (16 bytes).
For SHA1, hash output data is 160 bits (20 bytes.)
Input/Output data can start at any address. DES data length must be multiple of 64 bits.
Input/Output data can start at any address. AES data length must be multiple of 128 bits.
There are two XOR registers (upper and lower) to form 64 bits. The Cipher controller will perform an
Exclusive OR function between the fetch data (bypass mode) to these 64 XOR register bits. It then will
write back the result to the destination location. Note that, if XOR register bits are “0” then the output data
will remain the same.
In the Control Descriptor, bit 4 is a select bit for this feature (0: normal, 1: Select XOR mode 1).
Once XOR mode 1 is selected, the controller will fetch data from Input Source Address Descriptor and XOR
it with the data from XOR Input Source Address Descriptor 2 then it will write back this data to the Output
Destination Address Descriptor. In this mode, Output Byte Count and Input Byte Count must be the same.
26-2
Toshiba RISC Processor
TX4939
26
26