TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 694

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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CRYPT
26.2.2.2. CIPHER DMA Controller Registers
All registers are 32 bit. Firmware must use Word instruction to access to these registers.
26.2.2.3. Control and Status Register (CSR)
Rev. 3.1 November 1, 2005
Offset
Bit(s)
31:28
27
26
25
24
23
22:20
19
E0h-E8h
00h
08h
10h
18h
20h
28h
30h
38h
40h
48h
50h
58h
60h
68h
70h
78h
80h
88h
90h
98h
A0h
A8h
F0h
F8h
Field
SAESO
SAESI
SDESO
SDESI
--
INDXBST
TOINT
Register
CSR
IDESPtr
CDESPtr
BusErr
Cip_tout
Cir
Cdr1
Cdr2
Cdr3
Cdr4
Cdr5
Cdr6
Cdr7
Cdr8
Cdr9
--
--
--
--
--
--
--
--
XORSLR0
XORSUR1
R/W
RO
R/W
R/W
R/W
R/W
RO
RO
RO
Default
0
0
0
0
0
0
0
0
Width
Table 26-2 Control and Status Register (CSR)
Table 26-1 Cipher DMA Control Registers
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
--
--
--
--
--
--
--
--
Description
Reserved
Swap output AES data
0: Swap
1: No swap (for testing only)
For both Big or Little endian, this bit must be “0”.
Swap Input AESdata
0: Swap
1: No swap (for testing only)
For both Big or Little endian, this bit must be “0”.
Swap output DES data
0: Swap
1: No swap (for testing only)
For both Big or Little endian, this bit must be “0”.
Swap Input DES data
0: Swap
1: No swap (for testing only)
For both Big or Little endian, this bit must be “0”.
Reserved
Operate Index B Indicator
This field indicates the current operate index B register set
Time out Interrupt
0: No interrupt
1: Time out error
This bit will be clear after read.
R / W
R/W
R/W
R/W
R/W
R/W
R/W
WO
WO
WO
WO
WO
WO
WO
WO
WO
R
R
--
--
--
--
--
--
--
--
26-4
000
001
010
……..
110
111
Description
Control and Status Register
Initial Descriptor Pointer Register
Current Cipher Descriptor Pointer Register
Bus Error Address Register
Time out Register
Context Index Register
Context Data Register 1
Context Data Register 2
Context Data Register 3
Context Data Register 4
Context Data Register 5
Context Data Register 6
Context Data Register 7
Context Data Register 8
Context Data Register 9
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
XOR Source Lower Register
XOR Source Upper Register
Operating with Context register set #6
Engine idle
Operating with Context register set #1
Operating with Context register set #2
Reserved
……………………..
Toshiba RISC Processor
TX4939
26
26

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