TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 527

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
18.4. Registers
18.4.1. Overview
This subsection describes the Ethernet Controller registers you can access. These registers are grouped as follows
below.
During normal operation, once you finish setting them up, few registers require direct access. Transmission/Reception
operation is performed using a cyclic queue with a ring-like structure.
Control information and status information is transmitted by the data structures described in 18.3.7 Configuration. You
have to initialize the DMA Control Registers before starting any transfer operation.
You have to access the MAC Registers when it requires a special configuration such as address filtering by the ARC.
When using an interrupt drive type, you have to access several of the DMA Registers or MAC Registers from inside the
Interrupt Handler, enable or disable interrupts, check the interrupt factors, or clear the Interrupt Condition bit.
Also, the Flow Control Register can use a driver to access them in order to monitor the run status of Pause commands
issued from a local terminal or remote terminal.
18.4.1.1. Accessing registers
Except for those that use part of RAM, the reserved bits of a register are initialized to "0" or "1". To maintain compatibility
even if the method of using the registers changes in the future, do not change the values of the reserved bits when using
the software to write to registers.
Also, do not implement programming that depends on the values of the reserved bits.
18.4.1.2. Overview of PCI Configuration Registers
Table 18-7 lists the name, mnemonic, address, size, and access type of each PCI Configuration Register. PCI
Configuration Registers are used by standard Master/Slave PCI devices.
Included in PCI Configuration Registers are Device ID Registers, Control Registers, registers that display status
information, and registers that make various settings. These registers are setting during initialization.
The address of a PCI Configuration Register is valid when the input signal IDSel is asserted. The addresses of DMA
Registers and MAC Registers are valid when IDSel is not asserted and the upper bits of the addresses match either the
I/O Base Address Register (IO_BaseA) or the Memory Base Address Register (MLo_BaseA).
Rev. 3.1 November 1, 2005
PCI Configuration Register Group
DMA Control, Status Register Group
Flow Control Register Group
MAC Control, Status Register Group
Address
00h
02h
04h
06h
08h
0Ch
10h
14h
2Ch
2Eh
34h
3Ch
40h
44h
Mnemonic
Vend_ID
Dev_ID
PCI_Cmd
PCI_Stat
PCI_Clas
PCI_Ctl
IO_BaseA
MLo_BaseA
Sub_Vend_ID
Sub_ID
PCI_Cap_Ptr
PCI_Int
PM_Cap
PM_CSR
Table 18-7 PCI Configuration Registers
18-35
Register Name
Vendor ID Register
Device ID Register
PCI Command Register
PCI Status Register
Class Code Register
PCI Control Register
I/O Base Address Register
Memory Base Address Register
Subsystem Vendor ID Register
Subsystem ID Register
PCI Function Pointer
PCI Interrupt Register
Power Management Function
Power Management Control Status
Toshiba RISC Processor
TX4939
18
18