TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 13

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Index
CHAPTER 21. CIR CONTROLLER............................................................................................................................... 21-1
CHAPTER 22. I2C CONTROLLER ............................................................................................................................... 22-1
CHAPTER 23. I2S CONTROLLER ............................................................................................................................... 23-1
CHAPTER 24. ACLINK CONTROLLER ....................................................................................................................... 24-1
Rev. 3.1 November 1, 2005
20.4. R
21.1. F
21.2. B
21.3. F
21.4. R
22.1. O
22.2. I2C R
22.3. S
22.4. A
22.5. C
22.6. B
22.7. B
22.8. D
22.9. P
23.1. O
23.2. I2S F
23.3. DMA I
23.4. I
23.5. I
24.1. F
24.2. C
20.4.1. SPI Master Control Register (SPMCR)
20.4.2. SPI Control Register 0 (SPCR0)
20.4.3. SPI Control Register 1 (SPCR1)
20.4.4. SPI Interframe Delay Time Counter (SPFS)
20.4.5. SPI Status Register (SPSR)
20.4.6. SPI Data Register (SPDR)
21.3.1. Theory of Operation ................................................................................................................................... 21-3
21.3.2. Signal Muxing ............................................................................................................................................ 21-3
21.4.1. CIR Control/Status Register (CIR_CSR)
22.2.1. I2C Interrupt Control/Status Register (I2C_ICTSR)
22.2.2. I2C Transmit/Receive Register (I2C_TXRR)
22.2.3. I2C Command Register (I2C_CR)
22.2.4. I2C Prescale Register (I2C_PRE)
22.2.5. I2C Control Register (I2C_CTR)
22.3.1. I2C Protocol ............................................................................................................................................... 22-7
22.3.2. START signal ............................................................................................................................................. 22-7
22.3.3. Slave Address Transfer .............................................................................................................................. 22-7
22.3.4. Data Transfer ............................................................................................................................................. 22-8
22.3.5. STOP signal ............................................................................................................................................... 22-8
22.3.6. Arbitration Procedure ................................................................................................................................. 22-8
22.3.7. Clock Synchronization................................................................................................................................ 22-8
22.3.8. Clock Stretching ......................................................................................................................................... 22-9
22.6.1. Byte Mode:............................................................................................................................................... 22-10
22.9.1. Example 1 (Byte Mode)............................................................................................................................ 22-13
22.9.2. Example 2 (Byte Mode)............................................................................................................................ 22-14
23.2.1. I
23.2.2. Mode of operation ...................................................................................................................................... 23-6
23.2.3. MCLK and SCK Clock................................................................................................................................ 23-7
23.2.4. MCLK and WS Detection ........................................................................................................................... 23-8
23.3.1. Overview .................................................................................................................................................... 23-9
23.3.2. DMA Channel Mapping: ........................................................................................................................... 23-10
23.3.3. DMA Operation: ....................................................................................................................................... 23-10
23.4.1. Register Definition.....................................................................................................................................23-11
23.4.2. I2S Channel Main Control Register (I2SMCR)
23.4.3. I2S Channel Control Register (I2SCCR)
23.4.4. I2S Interrupt Control Register (I2SICTRL)
23.4.5. I2S Clock Option Register (I2SCOR)
2
NTERFACE
EATURES
UNCTIONAL
EATURES
LOCK
YSTEM
RCHITECTURE
YTE
IT
ROGRAMMING
S R
EGISTERS
EGISTER
LOCK
ATA
ONFIGURATION
VERVIEW
VERVIEW
C
OMMAND
IO S
EGISTER
UNCTION
2
C
EGISTER
S Interface ............................................................................................................................................... 23-3
NTERFACE
D
G
OMMAND
C
IAGRAM
ENERATOR
HIFT
ONFIGURATION
........................................................................................................................................................... 21-1
D
........................................................................................................................................................... 22-1
........................................................................................................................................................... 23-1
........................................................................................................................................................... 24-1
S
......................................................................................................................................................... 20-8
EFINITION
D
IGNALS
D
ESCRIPTION
C
..................................................................................................................................................... 23-3
D
R
.................................................................................................................................................... 22-9
E
EFINITION
ONTROLLER
EFINITION
.................................................................................................................................................. 21-2
C
EGISTER
.................................................................................................................................................. 23-9
.................................................................................................................................................. 24-2
XAMPLES
ONTROLLER
........................................................................................................................................... 22-10
........................................................................................................................................... 23-17
.......................................................................................................................................... 21-4
...................................................................................................................................... 22-7
................................................................................................................................... 22-12
....................................................................................................................................23-11
.................................................................................................................................... 21-3
.................................................................................................................................... 22-2
.................................................................................................................................. 22-13
............................................................................................................................... 22-12
............................................................................................................................ 22-10
0xF818 ................................................................................................. 20-14
0xF814 ................................................................................................ 20-13
0xF804 ......................................................................................... 20-10
0xF808 ..........................................................................................20-11
0xF920........................................................................................... 22-6
0xF908.......................................................................................... 22-4
0xF90C......................................................................................... 22-5
0xFA0C.................................................................................. 23-15
0xF800................................................................................... 20-9
0xFC00................................................................................ 21-4
0xFA04 .............................................................................. 23-12
ix
0xFA08............................................................................ 23-14
0xF80C ......................................................................... 20-12
0xF904 .......................................................................... 22-4
0xFA00 .......................................................................23-11
0xF900 .................................................................. 22-3
Toshiba RISC Processor
TX4939