TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 603

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

SPI
20.4.3. SPI Control Register 1 (SPCR1)
Rev. 3.1 November 1, 2005
Note 1: You can only write to bits 4, 2, 1, or 0 when the SPI Module is in the Configuration Mode.
Note 2: The SPOL and SPHA bits select the SPICLK phase and the clock edge at which to sample data. For details,
Bit(s)
1
0
Bits
31 : 16
15 : 8
7 : 5
4 : 0
Note 1: You can only write to this register when the SPI Module is in the Configuration Mode.
Default:
Default:
Name:
Name:
R/W:
R/W:
Bit:
Bit:
see 20.3.4
Mnemonic
SPHA
SPOL
Mnemonic
⎯
SER
⎯
SSZ
31
15
30
14
29
13
Field Name
SPI Phase
SPI Polarity
Field Name
Reserved
SPI Data Rate
Reserved
SPI Transfer
Size
28
12
0x00
SER
R/W
Figure 20-6 SPI Control Register 1 (SPCR1)
Table 20-5 SPI Control Register 0 (SPCR0)
Table 20-6 SPI Control Register 1 (SPCR1)
27
11
Description
⎯
SPI Data Rate (Default: 000000b)
This field sets the transfer bit rate. The transfer bit rate is calculated according to the
following equation.
f
f
n
⎯
SPI Transfer Size (Default: 00000b)
Selects the transfer size.
0x08: 8 bits
0x10: 16 bits
Other values: Reserved (not settings are permitted)
BR :
SPI :
Description
0: LSB first (transfer starting from the least significant bit)
1: MSB first (transfer starting from the most significant bit)
SPI Clock Phase (Default: 0)
Selects the clock phase.
0: Samples at the first clock edge, then shifts at the second edge.
1: Shifts at the first clock edge, then samples at the second edge.
SPI Clock Polarity (Default: 0)
Selects the SPICLK polarity.
0: High Active (SPICLK is Low when idle)
1: Low Active (SPICLK is High when idle)
26
10
(See 20.3.3 for SER and clock frequency examples.)
f
BR
SPICLK Frequency
SPI Master Clock Frequency
= f
:
25
SPI
9
SER (Setting “0” is not permitted)
20-11
/2 (n + 1)
RESERVED
24
8
23
7
RESERVED
22
6
21
5
20
Toshiba RISC Processor
4
19
3
0xF808
00000
R/W
SSZ
18
2
17
1
TX4939
16
0
20
20