TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 286

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

TMR
13.6.7. Pulse Generator Mode Register n (TMPGMRn)
Rev. 3.1 November 1, 2005
Bit
31:16
15
14
13:1
0
Default
Default
Name
Name
Type:
Type:
TMPGMR0 (0xF030), TMPGMR1 (0xF130)
Mnemonic
TPIBE
TPIAE
FFI
TPIB TPIAE
R/W
31
15
0
R/W
30
14
0
Field Name
Reserved
TMCPRB
Interrupt Enable
TMCPRA Interrupt
Enable
Reserved
Flip Flop Default
29
13
28
12
Figure 13-13 Pulse Generator Mode Register
Table 13-9 Pulse Generator Mode Register
27
11
Description
Timer Pulse Generator Interrupt by TMCPRB Enable (Default: 0)
When in the Pulse Generator mode, this bit sets Interrupt Enable/Disable for
when TMCPRB and the counter value match.
0: Mask
1: Do not mask
Timer Pulse Generator Interrupt by TMCPRA Enable (Default: 0)
When in the Pulse Generator mode, this bit sets Interrupt Enable/Disable for
when TMCPRA and the counter value match.
0: Mask
1: Do not mask
Initial TIMER Output Level (Default: 0)
This bit specifies the TIMER[n] signal default when in the Pulse Generator
mode.
0: Low
1: High
26
10
25
9
13-18
RESERVED
24
8
RESERVED
23
7
22
6
21
5
20
4
Toshiba RISC Processor
19
3
18
2
17
1
R/W
⎯
R/W
R/W
⎯
R/W
TX4939
R/W
FF1
16
0
0
13
13