TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 540
TX4939XBG-400
Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet
1.TX4939XBG-400.pdf
(740 pages)
Specifications of TX4939XBG-400
Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456
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EMAC
18.4.3.1. DMA Control Register (DMA_Ctl)
Rev. 3.1 November 1, 2005
Bit(s)
31 : 24
23 : 22
21 : 20
19
18
17
16
15
14
13
12 : 9
8 : 2
1 : 0
Default
Default
Name
Name
TYPE
TYPE
RxBigE TxBigE
R/W R/W R/W
31
15
Mnemonic
RxAlign
M66EnStat
IntMask
SWIntReq
TxWakeUp
TestMode
DmBurst
0
30
14
0
Mode
Test
29
13
0
Field Name
Reserved
Reception Alignment
Reserved
66 MHz Enable State
Interrupt Mask
Software Interrupt Request
Transmission Wake Up
Reserved
Reserved
Test Mode
Reserved
DMA Burst Size
Reserved
RESERVED
28
12
RESERVED
27
11
Figure 18-33 DMA Control Register
26
10
25
9
18-48
Description
D2Supp (Default: 0x0, R/W)
This field controls the alignment of reception packets as follows:
01: Skips the first byte of the first buffer.
10: Skips the first or second byte of the first buffer.
11: Skips the first through third byte of the first buffer.
M66EnStat (Fixed to 1, R)
1: Indicates that the PCI Bus operates at a maximum of 66 MHz.
0: Indicates that the PCI Bus operates at 33 MHz or less.
IntMask (Default: 0, R/W)
Setting this bit to “1” disables the interrupt request signal.
SWIntReq (Default: 0, R/W)
Setting this bit to “1” issues an interrupt request.
TxWakeUp (Default 0, R/W)
Setting this bit to “1” ends the current polling cycle and starts
transmission.
TestMode (Default: 0, R/W)
Enables the test mode function.
DmBurst (Default: 0x08, R/W)
Indicates the Burst size of data transfer executed in the Master
mode.
24
8
0x00
23
7
RxAlign
R/W
0x0
22
6
DmBurst
0x08
RESERVED
R/W
21
5
20
4
Toshiba RISC Processor
M66En
Stat
19
R
1
3
IntMask
R/W R/W R/W
18
0
2
SWIntR
17
eq
Reserved
0
1
TX4939
TxWak
eUp
16
0
0
18
18
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