TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 563

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
18.4.5.6. Address Recognition Circuit (ARC) Access Register
ARC Address Register (ARC_Adr)
Software resets initialize the ARC Address Register to 0x0000.
During normal operation, the ARC Address Register and ARC Data Register can perform read or write operation to all
ARC areas including two double-word positions immediately after flow control ARC. (See Figure 18-14.) During normal
operation, writes to all other memory positions are invalid.
When the TestMode bit of the DMA Control Register is set, you can use the ARC Address Register and perform read or
write operation on all RAM areas in the DMA Block.
Rev. 3.1 November 1, 2005
Bits
31 : 12
11 : 2
1 : 0
Default
Default
Name
Name
TYPE
TYPE
Mnemonic
ARC_Loc
31
15
RESERVED
30
14
Field Name
Reserved
ARC Address
Reserved
29
13
28
12
27
11
Figure 18-54 ARC Address Register
0x60
26
10
Description
ARC_Loc (Default: 0x00, R/W)
ARC address: 4 bytes
25
9
18-71
RESERVED
24
8
23
ARC_Loc
7
0x000
R/W
22
6
21
5
20
4
Toshiba RISC Processor
19
3
18
2
RESERVED
17
1
TX4939
16
0
18
18