TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 27

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Index
Rev. 3.1 November 1, 2005
Table 17-12 Parameters when Ultra DMA Transfer Ends ................................................................................... 17-31
Table 17-13 Parameters when Ultra DMA Transfer Starts .................................................................................. 17-32
Table 17-14 Parameters when Ultra DMA Transfer Ends ................................................................................... 17-33
Table 18-1 Usable eMAC channels based on Product Mode selection ................................................................. 18-2
Table 18-2 PCI Controller Control Registers.......................................................................................................... 18-5
Table 18-3 Frame Descriptor Format................................................................................................................... 18-15
Table 18-4 Buffer Descriptor Format................................................................................................................... 18-18
Table 18-5 Transmission Error Display (1/2)....................................................................................................... 18-29
Table 18-6 Reception Error Display .................................................................................................................... 18-30
Table 18-7 PCI Configuration Registers ............................................................................................................. 18-35
Table 18-8 DMA Control, Status Registers ......................................................................................................... 18-36
Table 18-9 Flow Control Registers...................................................................................................................... 18-36
Table 18-10 MAC Control, Status Register ......................................................................................................... 18-36
Table 18-11 Reception Control Register ............................................................................................................. 18-65
Table 18-12 Reception Status Register .............................................................................................................. 18-67
Table 19-1 Usable SIO channels based on PCFG settings ................................................................................... 19-3
Table 19-2 Example Divide Value Settings when using IMBUSCLK (and error [%] from target baud rate value) .. 19-6
Table 19-3 Example Divide Value Settings when using SCLK0 (and jitter value per bit time [%]) ........................ 19-6
Table 19-4 Example Divide Value Settings when using SCLK1 (and error [%] from target baud rate value) ......... 19-7
Table 19-5 SIO Registers ................................................................................................................................... 19-12
Table 19-6 Address offsets for Line Control Register in TX4939 ......................................................................... 19-13
Table 19-7 Line Control Register ......................................................................................................................... 19-14
Table 19-8 Address offsets for DMA/lnterrupt Control Register in TX4939 .......................................................... 19-15
Table 19-9 DMA/Interrupt Control Register.......................................................................................................... 19-16
Table 19-10 Address offsets for DMA/lnterrupt Status Register in TX4939.......................................................... 19-17
Table 19-11 DMA/Interrupt Status Register.......................................................................................................... 19-18
Table 19-12 Address offsets for Status Change Interrupt Status Register in TX4939 .......................................... 19-19
Table 19-13 Status Change Interrupt Status Register.......................................................................................... 19-19
Table 19-14 Address offsets for Fifo Control Register in TX4939 ........................................................................ 19-20
Table 19-15 FIFO Control Register...................................................................................................................... 19-20
Table 19-16 Address offsets for Flow Control Register in TX4939....................................................................... 19-21
Table 19-17 Flow Control Register ...................................................................................................................... 19-22
Table 19-18 Address offsets for Baud Rate Control Register in TX4939 ............................................................. 19-23
Table 19-19 Baud Rate Control Register ............................................................................................................. 19-23
Table 19-20 Address offsets for Transmit FIFO Register in the TX4939 .............................................................. 19-24
Table 19-21 Transmit FIFO Register.................................................................................................................... 19-24
Table 19-22 Address offsets for Receive FIFO Register in the TX4939............................................................... 19-25
Table 19-23 Receive FIFO Register .................................................................................................................... 19-25
Table 20-1 Selecting SPI as the active interface port in TX4939 ........................................................................... 20-3
Table 20-2 SPICLK Frequency .............................................................................................................................. 20-4
Table 20-3 SPI Module Registers .......................................................................................................................... 20-8
Table 20-4 SPI Master Control Register (SPMCR) ................................................................................................ 20-9
Table 20-5 SPI Control Register 0 (SPCR0) ........................................................................................................ 20-10
Table 20-6 SPI Control Register 1 (SPCR1) .........................................................................................................20-11
Table 20-7 SPI Interframe Delay Time Counter (SPFS) ...................................................................................... 20-12
Table 20-8 SPI Status Register (SPSR)............................................................................................................... 20-13
Table 20-9 SPI Data Register (SPDR) ................................................................................................................. 20-14
Table 21-1 CIR Control/Status Register ................................................................................................................. 21-4
Table 24-1 DMA Channel Mapping Modes ......................................................................................................... 24-10
Table 24-2 Front and Surround DMA Buffer Format in Little-endian Mode ..........................................................24-11
Table 24-3 Center, LFE, and Modem DMA Buffer Format in Little-endian Mode .................................................24-11
Table 24-4 Mic DMA Buffer Format in Little-endian Mode....................................................................................24-11
Table 24-5 Front and Surround DMA Buffer Format in Big-endian Mode ............................................................24-11
Table 24-6 Center, LFE, and Modem DMA Buffer Format in Big-endian Mode....................................................24-11
Table 24-7 Mic DMA Buffer Format in Big-endian Mode ......................................................................................24-11
Table 24-8 Transmission FIFO Depth ................................................................................................................. 24-13
Table 24-9 DMA Completion Status Determination............................................................................................. 24-13
Table 24-10 ACLC Registers .............................................................................................................................. 24-16
Table 24-11 ACCTLEN Register .......................................................................................................................... 24-17
Table 24-12 ACCTLDIS Register ......................................................................................................................... 24-21
Table 24-13 ACREGACC..................................................................................................................................... 24-24
Table 24-14 ACINTSTS Register ......................................................................................................................... 24-25
Table 24-15 ACSEMAPH Register....................................................................................................................... 24-28
Table 24-16 ACGPIDAT Register........................................................................................................................ 24-29
Table 24-17 ACGPODAT Register ....................................................................................................................... 24-30
Table 24-18 ACSLTEN Register .......................................................................................................................... 24-31
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Toshiba RISC Processor
TX4939