TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 8

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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Index
CHAPTER 10. NAND FLASH MEMORY CONTROLLER............................................................................................. 10-1
CHAPTER 11. REAL TIME CLOCK ...............................................................................................................................11-1
CHAPTER 12. VIDEO PORT......................................................................................................................................... 12-1
Rev. 3.1 November 1, 2005
10.1. F
10.2. B
10.3. D
10.4. ECC
10.5. R
10.6. T
11.1. F
11.2. RTC IP P
11.3. RTC IP R
11.4. T
12.1. F
12.2. B
12.3. O
9.4.1. ACE* Signal ................................................................................................................................................. 9-19
9.4.2. Normal Mode Access (Single, 16-bit bus) .................................................................................................... 9-20
9.4.3. Normal Mode Access (Burst, 16-bit Bus) ..................................................................................................... 9-22
9.4.4. Normal Mode Access (Single, 8-bit Bus)...................................................................................................... 9-23
9.4.5. Normal Mode Access (Burst, 8-bit Bus) ....................................................................................................... 9-25
9.4.6. Page Mode Access (Burst, 16-bit Bus) ........................................................................................................ 9-26
9.4.7. External ACK Mode Access (16-bit Bus)...................................................................................................... 9-27
9.4.8. READY Mode Access (16-bit Bus) ............................................................................................................... 9-32
9.4.9. ISA IO Space Access (16-bit only) ............................................................................................................... 9-33
10.2.1. Theory of Operation ................................................................................................................................... 10-2
10.3.1. Registers.................................................................................................................................................... 10-3
10.3.2. Convention for following explanation.......................................................................................................... 10-3
10.3.3. Accessing NAND Flash Memory (General Procedure) .............................................................................. 10-4
10.3.4. Initialization and UPDATE .......................................................................................................................... 10-5
10.3.5. Write Sequence (8-bit Bus, Program Mode) .............................................................................................. 10-6
10.3.6. Read Sequence (8-bit Bus, Program / DMA Mode) ................................................................................... 10-7
10.3.7. Read ID...................................................................................................................................................... 10-8
10.4.1. ECC Generation......................................................................................................................................... 10-9
10.4.2. ECC Data Format..................................................................................................................................... 10-10
10.4.3. DMA Operation ........................................................................................................................................ 10-10
10.4.4. Byte Sequence of DMA and ECC Generation...........................................................................................10-11
10.5.1. NAND Flash Memory Data Transfer Register (NDFDTR)
10.5.2. NAND Flash Memory Mode Control Register (NDFMCR) 0x5008 ......................................................... 10-14
10.5.3. NAND Flash Memory Status Register (NDFSR)
10.5.4. NAND Flash Memory Interrupt Status Register (NDFISR)
10.5.5. NAND Flash Memory Interrupt Mask Register (NDFIMR)
10.5.6. NAND Flash Memory Strobe Pulse Width Register (NDFSPR) 0x5028................................................. 10-17
10.6.1. Initialization Sequence ............................................................................................................................. 10-18
10.6.2. Data Read Sequence............................................................................................................................... 10-19
10.6.3. Data Write Cycles .................................................................................................................................... 10-20
11.2.1. RTC IP External Pin Description..................................................................................................................11-2
11.3.1. RTC IP Internal Registers............................................................................................................................11-3
11.3.2. RTC IP Control Registers ............................................................................................................................11-5
11.3.3. Control and Status Register (RTCCTL)
11.3.4. Address Register (RTCADR)
11.3.5. Data port to access the contents of RTC Register (RTCDAT)
11.3.6. Time Base Corrector Register (RTCTBC)
11.4.1. Theory of Operation ....................................................................................................................................11-7
12.3.1. Video Port DMA Controller ......................................................................................................................... 12-3
12.3.2. 8-bit Parallel port ........................................................................................................................................ 12-4
12.3.3. Serial port................................................................................................................................................... 12-5
12.3.4. Data Format ............................................................................................................................................... 12-6
12.3.5. Transmit Window Option ............................................................................................................................ 12-7
12.3.6. Video Port Controller Registers.................................................................................................................. 12-9
12.3.7. Descriptor Format .................................................................................................................................... 12-14
12.3.8. Big Endian Support .................................................................................................................................. 12-16
EATURE OF
IME
EATURES
IMING DIAGRAM
EATURE
LOCK DIAGRAM
LOCK
ETAILED
EGISTERS
PERATIONS
B
AND
ASE
D
IAGRAM
............................................................................................................................................................. 12-1
IN
EGISTERS
O
DMA O
........................................................................................................................................................... 10-1
C
PERATION
D
D
R
ALIBRATION
....................................................................................................................................................... 12-3
ETAIL
ESCRIPTION
EAL
.................................................................................................................................................. 10-2
................................................................................................................................................ 10-18
.................................................................................................................................................. 12-2
PERATION
T
............................................................................................................................................. 10-13
...............................................................................................................................................11-3
IME
........................................................................................................................................... 10-3
C
........................................................................................................................................11-7
LOCK
......................................................................................................................................11-2
.................................................................................................................................. 10-9
M
ODULE
(RTC).......................................................................................................11-1
0xFB04..................................................................................................11-6
0xFB00 ....................................................................................11-5
iv
0xFB0C................................................................................11-6
0x5010..................................................................... 10-15
0x5020 ........................................................ 10-16
0x5000 ........................................................ 10-13
0x5018 ....................................................... 10-15
0xFB08 ....................................................11-6
Toshiba RISC Processor
TX4939

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