TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 441

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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PCIC
16.4.59. PDMAC PCI Bus Address Register (PDMPA)
Rev. 3.1 November 1, 2005
Default
Default
Default
Default
NAME
NAME
NAME
NAME
Bits
63:38
39:2
1:0
TYPE
TYPE
TYPE
TYPE
Mnemonic
PDMPA
63
47
31
15
62
46
30
14
Field Name
Reserved
PCI Bus Address
Rsvd
61
45
29
13
RESERVED
60
44
28
12
Figure 16-70 PCI Bus Address Register
Table 16-72 PCI Bus Address Register
59
43
27
11
Description
PDMAC PCI-Bus Address (Default is undefined)
The PCI Bus DMA transfer address is specified by a PCI Bus physical
address on a 32-bit address boundary. This register value is held without
being affected by a Reset.
Note: This register value is used for PCI Bus Write access during DMA
transfer from the G-Bus to the PCI Bus, or it is used for PCI Bus Read access
during DMA transfer from the PCI Bus to the G-Bus.
58
42
26
10
PDMPA[15:2]
57
41
25
Undefined
9
16-77
R/W
PDMPA[31:16]
RESERVED
Undefined
56
40
24
8
R/W
55
39
23
7
54
38
22
6
53
37
21
5
PDMPA[39:32]
52
36
Undefined
20
Toshiba RISC Processor
4
R/W
51
35
19
3
50
34
18
2
49
33
17
Reserved
1
R/W
R/W
TX4939
48
32
16
0
16
16

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