TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 166

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

INTC
8.3. Detailed Explanation
8.3.1. Interrupt Sources
The TX4939 has 47 interrupt sources, such as interrupts from 44 types of on-chip peripheral circuits and 3 external interrupt
signals. Table 8-1 lists the interrupt sources and its interrupt numbers in the TX4939 system.
The priority encoder nominates highest priority interrupt and generates a 6-bit binary number corresponding to the interrupt
number in Table 8-1. This number always appears in the field of IRCS register. (i.e. IRCS.CAUSE)
The way to inform interrupt occurrence to CPU has variations depend on the interrupt operation mode.
8.3.2. Interrupt Operation Mode
TX4939 interrupt controller has two modes of operation. One is former TX49 Series compatible mode and TX4939 original
mode. These mode can be selected by setting the flag bit of “Interrupt Source and Cause IP Binding Register”. (See
8.4.2 )
8.3.3. Compatible Mode
In this mode, the interrupt occurrence will activate CP0 IP[2] bit only. This feature is upward compatible with former TX49
Series like TX4938. The interrupt handler is supposed to read IRCS.CAUSE register to get the interrupt number.
Addition to this feature, selected interrupt occurrences can be directly informed to CPU by means of CP0 IP[6:3] bit. The
assignment of interrupt source to designated IP bit can be performed by ISCIPB register.
(See 8.4.2 for detail explanation)
8.3.4. Original Mode
In this mode, the interrupt occurrence will activate CP0 IP[2] bit and CP0 IP[7:3], 5-bit will receive the interrupt number as
follows:
This structure created by simply expand TX4938 interrupt controller schema, which schema is only meaningful only when
the internal timer is not used.
To detect the occurrence of interrupt by checking CP0 IP[2] and then, the interrupt handler can get the interrupt source
number directly from CP0 IP[7:3] And if this register value is 31, interrupt handler is supposed to get exact interrupt source
number from IRCS.CAUSE register.
In addition to above interrupt sources, the TX49/H4 core has a TX49/H4 core internal timer interrupt and two software
interrupts, but these interrupts are directly reported to the TX49/H4 core independent of this Interrupt Controller. Please
refer to the 64-bit TX System RISC TX49/H4 Core Architecture Manual for more information.
Rev. 3.1 November 1, 2005
Note IRCS.CAUSE value never takes 31 by design.
If IRCS.CAUSE < 31, CP0 IP[7:3] <= (IRCS.CAUSE)
If IRCS.CAUSE > 31, CP0 IP[7:3] <= 31
8-4
Toshiba RISC Processor
TX4939
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