TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 542

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
18.4.3.2. Transmission Frame Pointer Register 0x04
Software resets initialize the Transmission Frame Pointer Register to 0x0000_0001.
Software resets set the EOL bit to “1”. To enable polling of a transmission or the packet to be transmitted, the system has
to set this register in a properly initialized frame descriptor. The address has to be aligned to a 16-Byte boundary.
Therefore, bits 0-3 must be “0”.
For information on polling control methods, see the description in 18.4.3.4 Transmission Polling Control Register.
Rev. 3.1 November 1, 2005
Bit(s)
31 : 4
3 : 1
0
Default
Default
Name
Name
TYPE
TYPE
31
15
Mnemonic
EOL
30
14
29
13
Field Name
Address
Reserved
End of List
Figure 18-34 Transmission Frame Pointer Register
28
12
27
11
26
10
0x000
R/W
Addr
25
9
18-50
Description
Addr (Default: 0x000_0000, R/W)
Retains the address of the first frame descriptor to be
transmitted.
EOL (Default: 1, R/W)
When this bit is set to “1”, the Address field is ignored. The
Ethernet Controller waits for the system to clear it.
24
8
0x000
Addr
R/W
23
7
22
6
21
5
20
4
Toshiba RISC Processor
19
3
RESERVED
18
2
17
1
TX4939
R/W
EOL
16
0
1
18
18