TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 194

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EBC
9.2.4.
SA [5:0] is dedicated address signal. The middle address will be provided through SADB [15:0].
External device latches the middle sixteen address bits and the upper six address bits by using the ACE* signal. Either the
ACE* signal itself can be used as a Latch Enable signal or the upper and middle address can be latched at the rise of
SYSCLK when the ACE* signal is being asserted.
The ADDR signal output is held for one clock cycle after the ACE* signal rise when the CCFG.ACEHOLD bit is set (default).
The ADDR signal output is not held when the CCFG.ACEHOLD bit is cleared. This hold time setting is applied globally to all
channels.
The ACE* signal of the upper address is always asserted for starting of every transaction. When there is a burst transfer,
ACE* signal is only asserted for the first cycle.
9.2.5.
In case of 16-bit data bus width mode, 512 MB memory space (2
When a Single cycle that accesses 1-Byte or 1 half-word data is executed, 16-bit access is executed only once on the
external bus. 16-bit access is executed twice when performing 1-word access. 16-bit access is executed four times when
performing 1-double-word access. When a Burst cycle is executed, four 16-bit cycles are executed for each Burst access
when the Bus cycle tries to request a byte combination other than double-word data.
9.2.6.
In case of 8-bit data bus width mode, 256 MB memory space (2
When a Single cycle that accesses 1-Byte data is executed, 8-bit access is executed only once on the external bus. 8-bit
access is executed twice when performing 1-half-word access. 8-bit access is executed four times when performing 1-word
access. 8-bit access is executed eight times when performing 1-double-word access. When a Burst cycle is executed, eight
8-bit cycles are executed for each Burst access when the Bus cycle tries to request a byte combination other than
double-word data.
Rev. 3.1 November 1, 2005
Latched SADB Bit
Middle Address
Middle Address
Latched SA Bit
Upper Address
Upper Address
Latched SADB
Latched SA
External Address Output
Address Bit Corresponding in the 16-bit Mode
Address Bit Corresponding in the 8-bit Mode
15
22
28
15
21
27
5
5
Table 9-4 Address Bit Correspondin in the 16-bit Mode
Table 9-5 Address Bit Correspondin in the 8-bit Mode
14
21
27
14
20
26
4
4
13
20
26
13
19
25
3
3
Note: Address is expressed by BYTE ADDRESS
Note: Address is expressed by BYTE ADDRESS
12
19
25
12
18
24
2
2
11
18
24
11
17
23
1
1
9-4
10
17
23
10
16
22
0
0
16
15
9
9
28
29
) is accessible. Table 9-5 shows this corresponding.
Non-latched SA
Non-latched SA
Lower Address
Lower Address
) is accessible. Table 9-4 shows this corresponding.
15
14
8
8
14
13
7
7
13
12
6
6
12
11
5
5
6
5
5
5
Toshiba RISC Processor
11
10
4
4
5
4
4
4
10
9
3
3
4
3
3
3
2
9
2
3
2
8
2
2
1
8
1
2
1
7
1
1
TX4939
0
7
0
1
0
6
0
0
9
9