TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 550

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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EMAC
"0", this indicates that the Ethernet Controller did not issue any interrupts. If the Ethernet Controller causes any interrupts,
then setting the IntMask bit of the DMA Control Register makes it possible to mask any subsequent interrupts that the
Ethernet Controller issues.
Bit 8 is set when there are more than 28 buffer descriptors are in a single frame descriptor. If excessive buffer descriptors
occur, the controller aborts transmission or reception operation. To resume transmission or reception operation, you have
to perform a software reset and rebuild the transmission queue, reception queue, and buffer list. Bit 13 is set when a
parity error is detected in the DMA RAM. However, bit 7 is only set if the DParErrEn bit of the Interrupt Enable Register is
set.
To make it possible to handle as many completed transmission frames or reception frames as possible, the software
driver has to clear the IntMACTx bit or the IntMACRx bit. Since the frame that is the interrupt source is handled as a part
of the immediately previous interrupt, there are cases where there are no complete frames in an interrupt. Take this into
account when creating your software driver.
Rev. 3.1 November 1, 2005
18-58
Toshiba RISC Processor
TX4939
18
18

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