TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 240

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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NDFMC
10.5.5. NAND Flash Memory Interrupt Mask Register (NDFIMR)
Rev. 3.1 November 1, 2005
Bits
31 : 8
7
6 : 1
1
0
INTEN
R/W
7
0
Mnemonic
INTEN
MDMA
MRDY
6
-
Figure 10-13 NAND Flash Memory Interrupt Mask Register (NDFIMR)
Table 10-8NAND Flash Memory Interrupt Mask Register (NDFIMR)
Field Name
Reserved
Interrupt Enable
Reserved
Mask
DMADONE
interrupt
Mask RDY
interrupt
5
RESERVED
Description
Interrupt Enable (Default: 0)
This bit enables interrupts. If INTEN bit are set to "1", an interrupt occurs when the
RDY or the DMADONE bit of the NDFISR Register becomes "1".
0: Disable
1: Enable
Mask DMADONE Interrupt (Default: 0)
This bit masks the DMADONE bit of the NDFISR Register. If this bit is “1”, the
DMADONE bit of the NDFISR Register is set when all the DMA requested byte have
been transferred to FIFO.
0: Disable the NDFISR DMADONE bit.
1: Enable the NDFISR DMADONE bit.
Mask Ready Interrupt (Default: 0)
This bit masks the RDY bit of the NDFISR Register. If this bit is "1", the RDY bit of the
NDFISR Register is set when the ND_RB* signal changes from "0" to "1".
0: Disable the NDFISR RDY bit.
1: Enable the NDFISR RDY bit.
4
10-16
3
2
MDMA
R/W
Toshiba RISC Processor
1
0
MRDY
R/W
0x5020
0
0
TX4939
: Default
: Type
10
10

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