TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 585

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

SIO
19.4.4. Status Change Interrupt Status Register 0,1,2,3
Rev. 3.1 November 1, 2005
Bit
31:6
5
4
3
2
1
0
31
15
Mnemonic
⎯
OERS
CTSS
RBRKD
TRDY
TXALS
UBRKD
(SISCISR0, SISCISR1, SISCISR2, SISCISR3)
Channel
SIO0
SIO1
SIO2
SIO3
Table 19-12 Address offsets for Status Change Interrupt Status Register in TX4939
Field Name
Reserved
Overrun Error
CTS Status
Receiving
Break
Transmission
Data Empty
Transmission
Complete
Break
Detected
Address Offset
0xF30C
0xF40C
0xF38C
0xF48C
Reserved
Figure 19-9 Status Change Interrupt Status Register
Table 19-13 Status Change Interrupt Status Register
⎯
Overrun Error Status (Default: 0)
This bit is immediately set to “1” when an overrun error is detected. This bit is
cleared when a “0” is written.
Receive Break (Default: 0)
This bit is set when a break is detected. This bit is automatically cleared when a
frame that is not a break is received.
1: Current Status is Break.
0: Current Status is not Break.
Transmit Ready (Default: 1)
This bit is set to “1” if at least one stage in the Transmit FIFO is free.
Transmit All Sent (Default: 1)
This bit is set to “1” if the Transmit FIFO and all transmission shift registers are
empty.
SIO Break Detect (Default: 0)
This bit is set when a break is detected. Once set, this bit remains set until cleared
by writing a “0” to it.
Description
CTS Terminal Status (Default: 0)
This field indicates the status of the CTS signal.
1: The CTS signal is High.
0: The CTS signal is Low.
This field is supported by SIO0 only.
Mnemonic
SISCISR0
SISCISR1
SISCISR2
SISCISR3
Reserved
19-19
Register Name
Status Change Interrupt Status Register 0
Status Change Interrupt Status Register 1
Status Change Interrupt Status Register 2
Status Change Interrupt Status Register 3
6
OERS CTSS
R/W0
C
5
0
R
4
0
RBRKD
R
3
0
TRDY TXALS
Toshiba RISC Processor
R
2
1
R
1
1
UBRKD
R/W0
16
C
0
0
: Initial value
: Initial value
Read/Write
⎯
R/W0C
R
R
R
R
R/W0C
: Type
: Type
TX4939
19
19