TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 173

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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8.4.2. Interrupt Source and Cause IP Binding Register (ISCIPB) 0xE808
Rev. 3.1 November 1, 2005
Bit(s)
31
30:24
23:16
15:8
7:0
CMM
R/W
31
15
0
30
14
Mnemonic
CMM
IP6BIND
IP5BIND
IP4BIND
IP3BIND
29
13
28
12
IP4BIND
R/W
IP6BIND
0
Field Name
Compatible Mode
IP[6] BIND
IP[5] BIND
IP[4] BIND
IP[3] BIND
Figure 8-5 Interrupt Source and Cause IP Binding Register
Table 8-7 Interrupt Source and Cause IP Binding Register
R/W
27
11
0
26
10
25
9
Explanation
Select Interrupt Controller Mode
0: Original Mode (Default)
1: Compatible Mode.
IP[6] interrupt source bind
This bit has an effect only in the “Compatible Mode”, which is activated
by setting “1” in CMM bit in this register.
In Compatible Mode, when the interrupt source N gets a request, the
request also propagates to CP0 IP[6] bit same time.
Note: Interrupt source number is defined in Table 8-1
0: No Assignment (Default)
N : Interrupt Source N (N>0) assigned this IP bit
IP[5] interrupt source bind
IP[4] interrupt source bind
IP[3] interrupt source bind
24
8
8-11
23
7
(Ditto)
(Ditto)
(Ditto)
22
6
21
5
20
IP5BIND
IP3BIND
4
R/W
R/W
0
0
19
3
18
2
Toshiba RISC Processor
17
1
16
0
: Default
: Default
: Type
: Type
TX4939
R/W
R/W
R/W
R/W
R/W
R/W
8
8

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