TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 203

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EBC
9.2.8.5.
The ACK*/Ready pin is used as a Ready input when in the Ready mode. The Ready input timing is the same as the ACK*
input timing explained in 9.2.8.4 ACK* Input Timing (External ACK Mode) with the two following exceptions.
Ready must be a High Active signal.
When in the Ready mode, the Wait cycle count specified by EBCCRn.PWT:WT must be inserted in order to delay the
Ready signal check (see 9.2.7.3 Ready Mode).
Rev. 3.1 November 1, 2005
ACK*/READY
ACK*/READY
SWE*/BWE*
SWE*/BWE*
SADB [15:0]
SADB [15:0]
AD [21:6]
AD [21:6]
SYSCLK
SYSCLK
SA [5:0]
SA [5:0]
ACE*
input
ACE*
input
Ready Input Timing
OE*
OE*
CE*
CE*
0
0
1
1
Start Ready Check / Acknowledge Ready
2
2
3
3
Acknowledge Ready
Figure 9-12 Ready Input Timing (Read Cycle)
Figure 9-13 Ready Input Timing (Write Cycle)
4
2 clocks
4
3 clocks
Ready Input Timing (Read Cycle)
Ready Input Timing (Write Cycle)
5
5
4 clocks
Latch Data
6
6
7
7
9-13
8
8
Start Ready Check
9
9
Start Ready Check
10
10
11
11
12
12
13
13
Acknowledge Ready
14
14
2 clocks
Acknowledge ACK*
Toshiba RISC Processor
15
15
3 clocks
Latch Data
16
16
4 clocks
17
17
18
18
19
19
TX4939
Rev 2.12
Rev 2.12
9
9