TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 77

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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Pin Assignment
3.3. Pin Function
Note:
indicates open drain. The asterisk "*" at the end of a signal name indicates that that signal is an Active Low signal.
3.3.1. System Clock and RESET Signals
3.3.2. DDR SDRAM Interface Signals
Rev. 3.1 November 1, 2005
System Clock and RESET Signals
Signal Name
MSTCLK
MSTCLK2
RESET*
HALTDOZE
IOSRST*
SYSRST*
DDR SDRAM Interface Signals
Signal Name
DRA[13:0]
DRDQ[31:0]
DRDQS[3:0]
DRDM[3:0]
DRCS[1:0]*
DRVref1
DRCKP,
DRCKM
DRCKOUT
DRCKREF
DRBA[1:0]
DRWE*,
DRCAS*,
DRRAS*
DRCKE
In the following table, "PU" in the I/O column indicates the presence of internal pull-up resistance, and "OD"
I/O
Input
Input
Input
Output
Output
Output
I/O
Output
I/O
I/O
Output
Output
Input
Output
Output
Input
Output
Output
Output
Function
Master Clock Input
20 MHz System Clock is required.
data processing.
Master Clock Input2
20 MHz System Clock is required.
UART Baud rate clock and Audio sampling clock. This clock should not be modulated
by external SSCG generator.
Reset
This is system-reset signal.
Halt/Doze Status Output
This signal is asserted (outputs the "H" level) when in either the Halt mode or the Doze
mode.
IO System Reset signal out
This pin is multiplexed with PCICLK[4] and can be used to reset external IO system
reset by software.
System Reset signal out
This pin is multiplexed with PCICLK[3] and can be used to reset whole system or
generate NMI to the CPU.
Function
Address
This address signals are for DDR SDRAM.
Data Bus
This is a 32-bit data bus dedicated for DDR SDRAM
DDR Control Signal for each byte data
DDR Control signal for each byte data
DDR Chip Select
DDR Voltage reference input
Differential DDR Clock Source
Single-end DDR Reference Clock for deskew
DDR Clock deskew reference input
DDR Bank Address
DDR Control Signals
DDR Control Signals
Clock Enable signal
This clock can be modulated by external SSCG generator.
3-5
This clock is used to generate internal clock for
This clock is used to generate internal clock for
Toshiba RISC Processor
TX4939
3
3

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