TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 452

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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PCIC
16.5.7. Power Management Control/Status Register (PMCSR) 0xE0
Rev. 3.1 November 1, 2005
Default
NAME
Bit
15
14:9
8
7:2
1:0
TYPE
Mnemonic
PMESTA
PMEEN
PS
R/W1C
PMESTA
0x0
15
14
Field Name
PME Status
Reserved
PME Enable
Reserved
Power State
13
12
11
PME_Status (Default: 0x0)
PME_En (Default: 0x0)
PowerState (Default: 0x0)
Description
Indicates the existence of a PME (Power Management Event) .
1: There is a PME.
0: There is no PME.
The value of this bit becomes “1” when Writing a “1” to the PME bit
(P2GCFG.PME) of the P2G Configuration Register.
This bit is cleared when the Host Bridge writes a “1”. It is possible to signal a
PME* Clear Interrupt at this time.
Sets PME* signal assertion to enable or disable.
1: Enables assertion of the PME* signal.
0: Disables assertion of the PME* signal.
The PME_En set bit of the P2G Status Register (P2GSTATUS.PMEES) is set
when this bit is set. At this time, it is possible to signal the PME_En set
interrupt.
Sets the Power Management state.
The Power Management State Change bit (P2GSTATUS.PMSC) of the P2G
Status Register is set when the value of this field is changed. It also becomes
possible to generate a Power State Change Interrupt at this time.
The TX4939an read the value of this field from the PowerState field
(PCISSTATUS.PS) of the Satellite Mode PCI Status Register.
00b: D0 (no change)
01b: D1 :Reserved
10b: D2 :Reserved
11b: D3hot
Figure 16-80 PMCSR Register
Table 16-83 PMCSR Register
10
9
16-88
PMEEN
R/W
0x0
8
7
6
RESERVED
0x0
5
Toshiba RISC Processor
4
3
2
1
R/W
R/W1C
R/W
R/W
TX4939
R/W
PS
0
16
16

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