TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 689

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

SRAM
25.4. Register
25.4.1. On-chip SRAM Control Register
Rev. 3.1 November 1, 2005
Default
Default
Default
Default
Type
Type
Type
Type
63:39
38:32
31:8
7:1
0
Bit(s)
63
47
19
31
15
SRBA [35:11]
SRSIZ [23:0]
CE
62
46
18
30
14
Mnemonic
61
45
17
29
13
000000000
SRSIZ[7:0]
60
44
16
28
12
On-chip SRAM Base
Address
Reserved
On-chip SRAM Size
Reserved
Channel Enable
SRBA[19:11]
0x00
R/W
R/O
Figure 25-3 On-Chip SRAM Control Register
Field Name
59
43
15
27
11
58
42
14
26
10
57
41
13
25
9
SRAM Base Address (Default: 0x0, R/W)
This field specifies the base address of on-chip SRAM. The upper 25
bits [35:11] of the physical address are compared with the value of this
field.
A 2-KB physical address space with the base address SRBA0[35:11] is
mapped to on-chip SRAM.
SRAM Size (Default: 0x00_0800, R/O)
Displays the on-chip SRAM size (2K Bytes).
Channel enable (Default: 0x0 , R/W)
This bit specifies whether to enable a channel. When using on-chip
SRAM, set "1".
0: Disable
1: Enable
25-3
SRBA[35:20]
SRSIZ[23:8]
56
40
12
24
8
0x0008
R/O
55
39
11
23
7
54
38
22
6
Description
53
37
21
5
RESERVED
52
36
20
4
Toshiba RISC Processor
RESERVED
51
35
19
3
0x6000
50
34
18
2
49
33
17
1
TX4939
R/W
CE
48
32
16
0
0
25
25