TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 586

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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SIO
19.4.5. FIFO Control Register 0,1,2,3
This register controls of the Transmit/Receive FIFO buffer.
Rev. 3.1 November 1, 2005
SWRST
Bit
31:16
15
14:9
8:7
6:5
4:3
2
1
0
R/W
31
15
0
(SIFCR0, SIFCR1, SIFCR2, SIFCR3)
Mnemonic
SWRST
RDIL
TDIL
TFRST
RFRST
FRSTE
14
Channel
SIO0
SIO1
SIO2
SIO3
Field Name Description
Reserved
Software
Reset
Reserved
Receive
FIFO
Request
Trigger
Level
Reserved
Transmit
FIFO
Request
Trigger
Level
Transmit
FIFO Reset
Receive
FIFO Reset
FIFO Reset
Enable
Reserved
Table 19-14 Address offsets for Fifo Control Register in TX4939
Address Offset
0xF310
0xF410
0xF390
0xF490
Software Reset (Default: 0)
This field performs SIO resets except for the FIFOs. Setting this bit to “1” initiates
the reset. Set registers are also initialized. This bit returns to “0” when initialization
is complete.
0: Normal operation
1: SIO software reset
Receive FIFO DMA/Interrupt Trigger Level (Default: 00)
This register sets the level for reception data transfer from the Receive FIFO.
00: 1 Byte
01: 4 Bytes
10: 8 Bytes
11: 12 Bytes
Transmit FIFO DMA/Interrupt Trigger Level (Default: 00)
This register sets the level for transmission data transfer to the Transmit FIFO.
00: 1 Byte
01: 4 Bytes
10: 8 Bytes
11: Setting disabled
Transmit FIFO Reset (Default: 0)
The Transmit FIFO buffer is reset when this bit is set. This bit is valid when the
FIFO Reset Enable bit (FRSTE) is set. Software has to clear this bit to start
normal operation.
0: During operation
1: Reset Transmit FIFO
Receive FIFO Reset (Default: 0)
The Receive FIFO buffer is reset when this bit is set. This bit is valid when the
FIFO Reset Enable bit (FRSTE) is set. Software has to clear this bit to start
normal operation.
0: During operation
1: Reset Receive FIFO
FIFO Reset Enable (Default: 0)
This field is the Reset Enable for the Transmit/Receive FIFO buffer. The FIFO is
reset by combining the Transmit FIFO Reset bit (TFRST) and Receive FIFO
Reset bit (RRST).
0: During operation
1: Reset Enable
Figure 19-10 FIFO Control Register
Table 19-15 FIFO Control Register
9
Mnemonic
SIFCR0
SIFCR1
SIFCR2
SIFCR3
Reserved
8
RDIL
R/W
00
19-20
7
Register Name
Fifo Control Register 0
Fifo Control Register 1
Fifo Control Register 2
Fifo Control Register 3
Reserved
6
5
4
TDIL
R/W
00
3
TFRST RFRST FRSTE
R/W
Toshiba RISC Processor
2
0
R/W
1
0
R/W
16
0
0
: Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
: Initial value
: Type
: Type
TX4939
19
19

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