TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 311

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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DMA
Rev. 3.1 November 1, 2005
Bit
6:3
2
1
0
Mnemonic
FIFUM[3:0]
RRPT
MSTEN
Field Name
FIFO Use Enable
[3:0]
Reserved
Round Robin
Priority
Master Enable
Table 14-7 DMA Master Control Register
Description
FIFO Use Enable [3:0] (Default: 0x0)
Each channel specifies whether to use 8-double word FIFO in Dual Address
transfer. FIFUM[n] corresponds to channel n.
Refer to “14.3.8.2 Burst Transfer During Dual Address Transfer” for more
information.
Round Robin Priority (Default: 0)
Specifies the method for determining priority among channels.
1:
lowest, and the next previous channel has the next lowest priority. Round
robin is in the order Channel 0 > Channel 1 > Channel > Channel 3.
0:
> Channel 2 > Channel 3.
Master Enable (Default: 0)
This bit enables the DMA Controller.
1: Enable
0: Disable
Note:
including the Bus Interface Logic and State Machine are reset.
Round Robin method. Priority of the last channel used is the
Fixed Priority. Priority is fixed in the order Channel 0 > Channel 1
If the entire DMA Controller is disabled, then all internal logic
14-23
Toshiba RISC Processor
R/W
R/W
R/W
R/W
TX4939
14
14

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