TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 633

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

I2S
23.3. DMA Interface
23.3.1. Overview
This section describes the mechanism for transmission and reception of I2S data. An overview is described first. The
DMA (Direct Memory Access) operation, error detection and recovery procedure follow.
Figure 23-8 and Figure 23-9 show conceptual views of the sample-data transmission and reception mechanisms.
Transmission or reception through each stream can be independently activated or deactivated under control of I2SC
Channel Control Register (start channel bits).
I2S controller is equipped with a separate FIFO for each channel. The data to transmit is prefetched from memory to FIFO
through DMA. The received data is buffered on FIFO and then stored to memory through DMA. In this stage, each DMA is
independently activated or deactivated under control of I2SC Channel Main Control Register (I2SMCR).
Rev. 3.1 November 1, 2005
Memory
Memory
Buffer
Buffer
DMA
DMA
Read
Write
Data
Data
Figure 23-8 Sample-data Transmission Mechanism
Figure 23-9 Sample-data Reception Mechanism
DMAC
DMAC
DMAREQ
DMAREQ
Write
Read
Data
Data
23-9
Latch
Latch
REQ
REQ
I2STLEN
Strobe
Strobe
Underrun Error
Overrun Error
I2SC
FIFO
I2SC
FIFO
Valid Flag
I2SLTEN
I2SLTEN
Toshiba RISC Processor
Data
Data
I2S
I/F
I2S
I/F
TX4939
23
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