TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 545

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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EMAC
18.4.3.5. Buffer List Frame Pointer (BLFrmPtr) 0x10
Software resets initialize the Buffer List Frame Pointer to 0x0000_0001.
When it fetches a free buffer descriptor, the Buffer List Frame Pointer holds the address of the first frame descriptor to be
read. To enable data reception, the system has to set this register in a properly initialized frame descriptor. The address
must be aligned to a 16-Byte boundary. In other words, bits 0-3 must be “0”.
Rev. 3.1 November 1, 2005
Bit(s)
31 : 4
4 : 1
0
Default
Default
Name
Name
TYPE
TYPE
31
15
Mnemonic
EOL
30
14
29
13
Field Name
Address
Reserved
End of List
28
12
Figure 18-37 Buffer List Frame Pointer
27
11
26
10
0x000
R/W
Addr
25
9
18-53
Description
Addr (Default: 0x000_0000, R/W)
EOL (Default: 1, R/W)
When this bit is set to “1”, the Address field is ignored. You have
to wait until the system clears this bit.
24
8
0x0000
Addr
R/W
23
7
22
6
21
5
20
4
Toshiba RISC Processor
19
3
RESERVED
18
2
17
1
TX4939
R/W
EOL
16
0
1
18
18

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